LX2160A COM Errata List

Revisions and Notes

Date	Owner	Revision	Notes
September 7, 2023	Josua Mayer	1.5	Release workaround for 1gbps ethernet activity led polarity
November 11, 2020	Rabeeh Khoury	1.4	SYSRESET# signal with regards PCBs rev 1.3..1.6 (and part of 1.7)
October 4, 2020	Rabeeh Khoury	1.3	Release information with regards PCB rev 1.6 and 1.7
March 29, 2020	Rabeeh Khoury	1.2	Release information with regards PCB rev 1.5
January 12, 2020	Rabeeh Khoury	1.1	Release information with regards PCB rev 1.4
November 12, 2019	Rabeeh Khoury	1.0	Released information

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Introduction

The intention of this document is to list erratas of SolidRun’s LX2160A based COM express type 7 module.

LX2160A- Rev 1.3 to rev 1.6 and partially PCB rev 1.7 Errata

Short Description

Errata

Affected PCB rev

Fix or workaround

LX2 COM express SYSRESET# input signal

LX2 COM express SYSRESET# signal was implemented with a bi-directional level shifter as input for the COMe. The level shifter gets “confused” when assembling capacitors due to it’s internal single shot implementation and might create a “reset loop” condution, or system not booting that the reset button must be clicked.

The affecting capacitor on the COM express is C3, refer to the image below (*)

1.3 to 1.6, part of 1.7

The workaround is to disassemble C3 from the COM express (and C94 on the HoneyComb / ClearFog CX PCBs)

The fix is already implemented on part of the PCB rev 1.7, when the issue was found debugged and deployed.

Future revisions will not have C3 assembled.

(*) Below is an image showing the placement of C3 capacitor on all boards up to rev 1.6 between the reset button and the boot DIP switch.

LX2160A- Rev 1.3 to rev 1.6 Errata

Short Description	Errata	Affected PCB rev	Fix or workaround

Short Description

Errata

Affected PCB rev

Fix or workaround

LX2 SoC production long term reliability

LX2 long term reliability testing showed the requirement of the below modification, in board level. Those issues were not observed in the lab, but only on long term reliability testing (by NXP) –

Use SD / micro SD interface 1.8 to 3.3v level shifter instead of using the native 1.8/3.3v tolerence.
Pull up USB1_VBUS and USB2_VBUS to 5V instead of shorting it to 5V.

1.3 to 1.6, fixed in 1.7

No software modifications required to support the level shifter in rev 1.7.

No valid hardware or software workarounds to accomodate those issues in PCBs rev 1.3 .. 1.6

LX2160A- from rev 1.5 to rev 1.6 feature enhancement

Short Description

Feature

Affected PCB rev

This is not an errata but addition of a feature

Added 1588 signals by wiring those signals to the 10G_SDP* signals of COM with addition of using few reserved pins.

Note that all those signals are coming directory from the processor and are 1.8v voltage level.

1.5, addition reflected in rev 1.6

LX2160A- Rev 1.4 Errata

Short Description

Errata

Affected PCB rev

Fix or workaround

AMC6821 FAN controller PWM-OUT signal pull-up

Missing pull-up on AMC6821 FAN controller PWM-OUT signal output that is connected to Q5. On all rev 1.4 PCBs that are shipped RN21 resistor pack pin 4, which is unused is wired to the PWM-OUT signal by a wire jumper.

Rev 1.5 of the PCB fixes that wire.

1.4, fixed in 1.5

Fix already implemented on all rev 1.4 PCBs by wiring RN21 pin 4 to PWM-OUT signal. Rev 1.5 fixes that on the PCB itself which makes it software compatible to PCB rev 1.4.

LX2160A- Rev 1.3 Errata

Short Description	Errata	Affected PCB rev	Fix or workaround
Boot from SPI not supported	Reading RCW values and initial boot image from SPI ROM is not supported since the SPI ROM is connected HRESET_B signal instead of POR_RESET_B	1.3, fixed in 1.4	Issue is fixed rev 1.4. For rev 1.3 users as a workaround – boot RCW from SD and use SPI ROM in runtime (u-boot/kernel/UEFI variable storage etc…)
FAN PWM signal not functional	FAN controller in rev 1.3 is not assembled since it’s control has the wrong polarity.	1.3, fixed in 1.4	Issue is fixed rev 1.4. For rev 1.3 users – to lower noise levels of a fan use lower CFM fan, or different brand or low-noise adapter cable that lowers the 12v input to the fan. Notice that SolidRun ships a low-noise adapter cable with each system that has rev 1.3.
FAN TACH signal missing pull-up	Although FAN controller is not assembled in rev 1.3; the FAN TACH signal is not pulled up on the COM module.	1.3, fixed in 1.4	Issue is fixed rev 1.4. Rev 1.3 users must add a pull-up to 3.3v via 10kohm resistor.
SPI_CS# signal missing pull-up	External bootable SPI ROM CS# is not pulled-up on COM module.	1.3, fixed in 1.4	Issue is fixed in rev 1.4. Rev 1.3 users must add a pull-up to 3.3v via 10kohm resistor.
CFG_RCW_SRC0 and CFG_RCW_SRC1 pull-up	CFG_RCW_SRC0 and CFG_RWC_SRC1 has an in-LX2160A SoC internal pull-up. This pull-up is not functional after changing their function to UART0/1 TX; due to that booting from SD and then booting from different source that requires using the LX2160A internal pull-up will capture the wrong boot source.	1.3, fixed in 1.4	Issue is fixed in rev 1.4.
I2C level shifter signal reflection	1.8v to 3.3v I2C level shifter on the COM express module has a high rise time which creates a reflection on the 3.3v domain. In rare occasions this reflection might create a signal dip on the I2C clock signal that might get interpreted wrongly as a clock rise.	1.3, fixed in 1.4	Issue is fixed in rev 1.4 by adding a damping resistor. As a symptom to this issue when booting and I2C SPD eeproms are not read correctly.
MDC/MDIO level signal reflection	1.8v to 3.3v open-drain level shifters used to MDC/MDIO signals level shifting has high rise time which creates signal reflection on both signals. The critical signal is the clock and it’s connected to the on COM 1Gbps phy and the COM express headers on C16 and and C46 COM headers. When C16 and C46 are not used they can reflect the clock that will disturb the rising edge of the clock on the 1Gbps phy and thus creates wrong reads from the phy and loosing the link since the kernel polls the phy’s register regularly	1.3, fixed in 1.4	Issue is fixed in rev 1.4. Rev 1.3 users are required to add a 49.9 ohm and 150pF RC filter. If a new carrier board is being designed add this RC filter near C16 COM express header (EMI1…MDC).
GPIO level shifters are not functional	GPIO level shifters for the below signals are not fully functional. Due to the issue part of the GPIO signals can function only as input, part as output and part are not functional. Input only – 10G_INT0, 10G_INT1, 10G_INT2, 10G_INT3, GPO2, PWRBTN# Output only – SUS_S5# Non functional – BATLOW#, SMB_ALERT#, THRM#, P01_10G_PHY_RESETN, P12_10G_PHY_RESETN.	1.3, fixed in 1.4	Issue is fixed in rev 1.4
micro SD write-protect	LX2160A wire-protect signal is left floating in rev 1.3 since it is not used in a micro-SD setup and it is not possible to configure the controller to disregard that signal. Due to that writing to SD flash (micro SD when using Clearfog CX/HoneyComb) is not supported.	1.3, fixed in 1.4	Issue is fixed in rev 1.4
LED_ACT inverted polarity	LED_ACT Signal on CEX-7 connector is defined as active-low. On LX2160A-CEX-7 module however this signal behaves like active-high. It can be observed e.g. on Clearfog CX Carrier that the LED is on by default without cable connected.	all versions	Can be fixed based on MoQ. Workaround: signal polarity depends on bootstrap configuration of ethernet phy via pull-up/pull-down resistors. R89 (assembled by default) can be disassembled. See location in picture below (**). This change affects ethernet phy address, which will change from 1 to 5. Updates are required to both U-Boot and Linux.

(**) below location of R89 for activity led polarity workaround: