OPENBMC Module Hardware Integration Manual


The purpose of this document is to provide hardware integration manual for SolidRun’s OpenBMC based products.

The manual focuses on using different flavours of SolidRun’s ready to use system on modules (SOMs) where the differentiation between them is feature set and cost structure.

The main two SOMs mentioned in this manual are SolidRun’s Renesas G2L and SolidRun’s NXP i.MX8M-mini where the hardware designer can design a PCB that uses the same 3 Hirose DF40 board to board headers and swap between different SOMs while balancing the required features, performance, thermal and price points.

Both of those SOMs have same placement and count of the 3 board to board headers (J7+J9 are each 80 pin and J5001 is 70 pin). When comparing the pinout of those two modules it is noticeable that most of the functions are shared between the different SOMs, but there are also differences that mainly comes from the fact that different SoCs are being used; so different features are supported.

Common hardware integration manual

SolidRun intends to base the BMC on RZ/GL2 SOM

The assumption is the the hardware developer is intimately familiar with the following document -

The features of RZ/GL2 are:

  1. Dedicated out-of-band 1Gbps Ethernet interface

  2. 2x null-modem UART interfaces:

    1. BMC serial console

    2. Host connection

  3. 10x GPIOs for host power button, reset and other functions

  4. 1x I2C for FRU audit to be used further-on for inventory and logging

  5. 1x USB device mode (or OTG) to be connected to host

  6. -40ºC to 105ºC CPU junction temperature

  7. SPI interface for flashing host BIOS

The following common features of the different SOMs are to be used -

  1. Always on 5V input to SOM via J9 pins 71,73,75,77,79

  2. 3.3V BMC console via J7 pins 52/54 BMC UART TX / RX respectively. This gets mapped to SCIF_4 on G2L and UART2 on i.MX8M-mini

  3. 3.3V BMC to host UART via J7 pins 38/44 BMC TX/RX, Host RX/TX. This gets mapped to SCIF_2 on G2L and UART3 on i.MX8M-mini

  4. 3.3V BMC I2C on J9 pin31/33 as SCL/SDA. This gets mapped to I2C_0 on G2L and I2C3 on i.MX8M-mini

  5. Additional 3.3V BMC I2C on J9 pin 53/51 as SCL/SDA. This gets mapped to I2C_1 on G2L and I2C2 on i.MX8M-mini

  6. USB 2.0 OTG from BMC to host on J9 pins 16/18 (DP/DN). This gets mapped to USB0 on both SoCs.
    Additional OTG ID is on J5001 pin 48 for G2L and pins 56 on J7.
    Additional USB VBUS on J9 pin 43 (5V)

  7. Bootable micro-SD for development thru J9 pins 38,40,42,44,46,48,50. Voltage level is either 1.8v / 3.3v and controlled by SOM.

  8. Boot switches (TBD)

  9. 1 Gbps Ethernet MDI interface (1 Gbps PHY on SOM) via J9 pins 1,3,7,9,13,15,19,21,25,27

  10. 3.3v SPI interface for host BIOS via J9 pins 49,45,47,32 CLK/MISO/MOSI/CS0. This gets mapped to RSPI1 on G2L and ECSPI_2 on i.MX8M mini

Following is a table that summarizes all the above mappings -


Pin numbering

Mapping to Renesas G2L SOM

Mapping to Renesas G2LC SOM

Mapping to NXP i.MX8M mini SOM


Pin numbering

Mapping to Renesas G2L SOM

Mapping to Renesas G2LC SOM

Mapping to NXP i.MX8M mini SOM

Main supply 5v

J9 pins 71,73,75,77,79




SOM 3.3v supply (output from SOM)

J9 pins 63,65,67,69)

PMIC supply from SOM for carrier peripherals

PMIC supply from SOM for carrier peripherals

PMIC supply from SOM for carrier peripherals

BMC Console (3.3v)

J7 pins 52,54




BMC to Host #1 UART (3.3v)

J7 pins 38,44




BMC to Host #2 UART (3.3v)

J5001 pins 46,44




FRU I2C (3.3v)

J9 31,33




Additional I2C (3.3v)

J9 53,51




USB 2.0 Device

J9 pins 16,18




Micro-SD for Development

J9 pins 38,40,42,44,46,48,40




1 Gbps Ethernet

J9 pins 1,3,7,9,13,15,19,21,25,27

SoC MAC + 1 Gbps PHY

SoC MAC + 100Mbps PHY

SoC MAC + 1 Gbps PHY

SPI Interface

J9 pins 49,45,47,32





J7 pins 10, 18, 20, 26

J9 pins 34

RZ_P42_2,P17_0,P17_1, P39_1





Boot select

J5001 3,5,41

MD0, MD1 and MD2 (1.8v)

MD0, MD1 and MD2 (1.8v)

BOOT_MODE0 and BOOT_MODE1 (1.8v)

Integrating the SOM as BMC instructions step-by-step

Following are instructions on how to integrate the SOM used as BMC into a custom design -

  1. The SOM size is 47x30 mm. It is recommended to study the HummingBoard pulse schematics and layout which is used as a development carrier board for the SOMs specified above.

  2. All 3 board to board headers are required for a functional system.

  3. Supply the SOM with fixed always-on 5.0v -/+ 5% to J9 pins 71,73,75,77,79 with peak current of 1.5A (peak 7.5W).

  4. Connect the 3 boot select pins J5001 3,5,41 to a DIP switch that is 1GND 4.7k/10k ohm pull-down connected

  5. Connect BMC console J7 pins 52 (TX) and 54 (RX) to a 3 pin header (TX,GND,RX). This is mainly used for bring-up, debug and development and not required to be assembled in mass-production.

  6. Connect Micro-SD pins (J9 pins 50,38,40,42,44,46,4) to a micro-SD connector. This is mainly used for bring-up, debug and development and not required to be assembled in mass-production where the openbmc firmware can be flashed by the customer either through HummingBobard board, or by SolidRun.

  7. Connect Ethernet MDI signals (J9 pins 1,3,7,9,13,15,19,21,25,27) to magnetics that is connected to RJ45 (main interface to the BMC).

  8. Connect BMC to Host #1 UART J7 pins 38,44 to host UART directly if the host I/Os are 3.3v or through a 3.3v / 1.8v level shifter. The supply to the level shifter is recommended to be supplied from the SOM 3.3v output

  9. Connect BMC USB0 device mode J9 pins 16,18 to host USB 2.0 host mode. This is used for BMC virtual media function.

  10. Connect 3.3v SPI interface to host flash mux via J9 pins 49,45,47,32 where GPIO J7 pin 10 is used as MUX select. If the host flash is 1.8v then use a 3.3v to 1.8v level shifter and the CS signal as output enable for that level shifter.
    The supply to that level shifter is recommended to be supplied by the SOM 3.3v output.
    If the host flashing subsystem provides complete offline programming (i.e. voltage to mux/flash is supplied when host is powered down); then provide that voltage also directly from the SOM supplies (i.e. directly 3.3V or through 3.3V to 1.8V LDO).

  11. Connect I2C J9 31,33 3.3v signals to system FRU EEPROM directly or through I2C level shifter. Notice that by default that EEPROM uses address 0x50.

  12. Connect I2C J9 53,51 to system telemetry and sensors.

  13. Connect J7 pin 20 for an N-channel MOSFET that enables main supply to the host when 1 logic (3.3v voltage level). When logic 0 (i.e. GND) the main supply must be disconnected.
    It’s possible to connect the same pin for one of the stages of the DC-DC power supplies oh the main host.
    Note that this pin MUST be pulled down via 1k ohm to GND to forbid host going on when the BMC is booting.

  14. Connect J7 pin 18 GPIO to any indication that the host processor provides that it’s ON. For instance through an N-channel transistor connected to host S0 state, or power LED.
    Note that this pin MUST be pulled down via 1k ohm to GND to indicate host powered down when not driven.

  15. Connect J7 pin 26 to host edge or level active low reset input via a P-channel MOSFET.

  16. Connect J9 pin 34 to the gate of N-channel transistor where when active high it will ground and discharge the host CPU RTC power input (typically the RTC 1k ohm safety series resistor and the input of the RTC ORing schotkey diode).
    Notes -

    1. The gate to the above N-channel transistor MUST be pulled down via 1k ohm to GND to keep the RTC well connected.

    2. The source of the transistor must be connected AFTER the safety RTC battery series 1k ohm to forbid shorting the battery to GND.

    3. This feature is functional only when the host CPU is off. The reason is that typically the ORing schotkey diode is feed from the RTC battery and a 3.3v power domain.

  17. (Optional for development) - BMC reset - Connect J7 pin 65 to a micro switch, or header that when triggered connects this signal to GND.
    Note - do not pull-up this signal to any power domain since it’s properly pulled on the SOM.

GPIO mapping

GPIO Number


GPIO Number


J7 pin 10

SPI host flash programming / mux select

J7 pin 12

Host power button sensing

J7 pin 14

Host power button control

J7 pin 18

Active high Host is on (POST Complete)

J7 pin 20

Active high host/chassis power switch

J7 pin 22

Host/chassis power good

J7 pin 26

Active low host reset. On negative edge (3.3v to GND) this circuit triggers host system reset via P-channel MOSFET

J7 pin 28

Host reset button sensing

J7 pin 30

BMC_LED0 (BMC booted)

J7 pin 32

BMC_LED1 (BMC identify)

J7 pin 34

BMC_LED2 (Host powered)

J7 pin 36

BMC_LED3 (host ok/fault)

J9 pin 34

Active high host RTC battery disconnect. This signal is active high and when transisions from GND to 3.3v it grounds the RTC power input to the main processor via an N-channel MOSFET. This transistor MUST be connected after the safety 1K ohm between the battery and the RTC power input.

Prototype using HummingBoard

The prototype intention is to use HummingBoard that includes one of the above two SOMs as a prorotype vehicle to wire part of it’s signals to the host SBC.

The following signals can be easily exposed and wired to the host SBC -


HummingBoard wireup


HummingBoard wireup

BMC console

Use HB micro USB to serial

Host console

Use Mikrobus UART TX/RX that are connected to J5001 pins 29/31 (3.3v)


TBD (Add external I2C EEPROM thru MikroBus that goes to J9 31,33)


Use MikroBus interface to connect to host SPI flash (3.3v)

USB 2.0 device

Use HB upper USB 2.0 host with a host-to-host cable

Micro-SD for development

Use HB micro SD

1Gb for out-of-band management

Use HB 1Gb RJ45 (CON1)

Alternative implementation of BMC based on i.MX8M mini


i.MX8M Mini SOM has all the relevant features of RZ/CL2.

Additional features supported by i.MX8M Mini SOM:

  1. PCIe gen2 x1 via J7 pins 1,2,3,4,7,9 - Can be used for connecting external 2.5 Gbps Ethernet controller


SolidRun Ltd.