AM64x SOM Hardware User Manual

Revisions and Notes 

Introduction

This User Manual relates to the SolidRun SR-SOM-AM64xx-series, which includes

• Single/Dual core ARM A53 (1.0 GHz).

• Single/Dual cores Cortex®-R5F 800 MHz processor.

• A general-purpose Cortex®-M4F 400 MHz processor.

Overview

The SolidRun’s SR-SOM-AM64xx is a low power, low-cost high performance micro system on module (S.O.M.) based on the highly integrated TI's AM64xx family of products targeting the Industrial Market Applications.

Highlighted Features

• Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number).

• TI's AM64XX SoC:
  -  Single/Dual core Cortex A53 up to 1.0GHz
  -  400 MHz Cortex-M4F subsystem processor supports real time tasks.
  - Up to two dual-core Cortex-R5F MCU subsystems at up to 800 MHz, integrated for real-time processing.
  - Safety & Security engines

• DDR4 (1.6 GHz) memory in x16 configurations supports up to 2GB and inline ECC

• Up to two 1GB Ethernet port supporting Industrial Ethernet protocols.

• Single Gigabit Ethernet interface.

• Two ports TSN GE switch.

• Industrial IO supports – CAN, RS-485 etc.

• Single PCIe Gen 2 or USB 3 interface.

• Low latency interfaces to motor control front.

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard AM64x– A board computer that incorporates the SOM retains the same Linux distributions while adding extra hardware functionalities and access to the hardware.

Description

Block Diagram

The following figure describes the AM64xx SOM's Blocks Diagram.

Features Summary

Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table and the TI's AM64xx data sheets):

·         Dual/Single ARM® Cortex™ A53 Processor, up to 1.0 GHz

·         Dual or single dual-core Cortex R5F Up to 800 MHz

·         Cortex-M4 subsystem processor up to 400 MHz

·         Up to 2GByte DDR4 memory

·         Up to 64 GB eight bits eMMC memory.

·         OSPI/QSPI NOR Flash memory.

·         I2C EEPROM.

·         Up to 3 x 10/100/1000 Mbps Ethernet PHY

o   Up to two gigabit Industrial Communication Subsystems e.g., ECAT, Profinet etc.

o   Time stamping

o   TSN

·         SUB Giga modem (CC1312)

·         Variety of interfaces and IO on Board-to-Board connectors.

A single 5.0V interface

Core System Components

AM64xx Sitara SoC Family

The AM64xx Sitara processors feature advanced implementation of a duad Arm® Cortex®-A53 core, which operates at speeds of up to 1.0 GHz. A general-purpose Cortex®-M4 core processor is for low-power processing and two dual-core Cortex-R5F supporting industrial protocols.

The following figure describes the AM64xx main features (For more details refer to TI’s AM64x datasheet).

Memories

The AM64xx SOM supports varieties of memory interfaces for booting and data storage. The following figure describes the AM64xx SOM memory interfaces.

DDR4

• Up to 2GB memory space.

• 16 Bits data bus.

• Up to 1600 MT/s.

• Inline ECC.
  
  

 eMMC NAND Flash

 Up to 64GB memory space.

• 8 Bits data bus.

• Support of eMMC5.1 Host Specification (JESD84-B51).

• HS200 SDR: 1.8 V, 0-200 MHz, 8/4-bit bus width, 200/100 MB/s

• HS400 DDR is NOT supported.

• Can be used as BOOT NVM *

 Octal Serial NOR Flash (SOM)

• Supports 1/2/4 or 8-bit operation.

• Support for DDR Mode and DTR protocol.

• Programmable device sizes

• DMA NOT supported.

• In Octal-SPI and Quad-SPI mode, Mode 1, 2, and 3 are NOT supported.

• Can be used as BOOT NVM *

EEPROM (SOM)

 ·       1Kb EEPROM

·       ON-Semi’s CAT24AA01TDI or compatible

·       Address 0X50 (7 bits format)

·       Stores SOM’s configurations.

Micro-SD (Carrier)

 ·        Optional on Carrier board

·        Implements 4 data bits.

·        SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01.

·        SDIO Specification v3.00

·        DDR50: UHS-I 1.8 V signalling, frequency up to 50 MHz, up to 50 MBps.

·        SDR104 is NOT supported.

·        Can be used as BOOT NVM *

10/100/1000 Mbps Ethernet Interfaces

The AM64xx SOM supports three Giga-Ethernet interfaces. One of the interfaces is connected directly to the Ethernet switch (CPSW3G) and the two others are part of the Programmable Real-Time Unit and Industrial Communication Subsystem – Gigabit (PRU_ICSSG). The following figure describes the Ethernet port interfaces.

The three Giga Ethernet PHY are TI’s DP83869:

• Low RGMII Latency

• Low Power Consumption

• Time Sensitive Network (TSN) Compliant

• IEEE1588 Support

• Cable Diagnostics

• Recovered Clock Output for SyncE

• MDI or MDIX support.

PRU_ICSSG

• Two Real-Time Ethernet ports.

• MDIO port to control external Ethernet PHY

• Time Stamping support.

• Industrial protocols used in master and slave mode, such as:

o   EtherCAT®

o   PROFINET™

o   EtherNet/IP™

o   Others

CPSW3G

• Single Giga Ethernet port

• Synchronous 10/100/1000 Mbit operation

• MDIO port to control external Ethernet PHY

• Support for Audio/Video Bridging (P802.1Qav/D6.0 and 802.1Qaz)

• Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)

• IPV4/IPV6 UDP/TCP checksum offload.

Clock Chaining

The following figure describes the Ethernet reference clock configuration.

The 25Mhz clock source is the CPU’s CLOCOUT1 signal. It is connected to the CPCW3G Ethernet PHY.

ICSSG1 clock is connected to CPSW3G output clock and ICSSG2 is connected to ICSSG1 clock.

AM64xx External Interfaces

General 

The SOM incorporates three Hirose DF40 board-to-board headers.

The selection of the Hirose DF40 is due to the following criteria:

·         Miniature (0.4m pitch)

·         Highly reliable manufacturer

·         Availability (worldwide distribution channels)

·         Excellent signal integrity (supports 6Gbps)

o   Please contact Hirose or SolidRun for reliability and test result data.

·         Mating height of between 1.5mm to 3.0mm. AM64xx headers are fixed, the final mating height is determined by carrier implementation

Supported Interfaces - Main

PCIe & USB3

The AM64xx supports a single Ser/Des interface. The Ser/Des can be configured as a PCIe or a USB3.0 interface. The following figure describes the optional Ser/Des configurations.

The PCIe main features are:

·         Ser/Des is configured as PCIe.

·         On board coupling capacitors for TX and CLK.

·         PCIe clock is generated on the AM64xx SoC.

·         Single PCIe lane up to 5.0GT/lane.

·         Gen2 (5 Gbps 8/10-bit encoding), and Gen1 (2.5 Gbps 8/10-bit encoding) with auto-negotiation.

·         Compliant to PCI-Express® Base Specification, Revision 4.0 (Version 0.7).

·         PHY Interface for the PCI Express Architecture, Version 4.2 compliance.

·         Supports Spread Spectrum Clocking in Transmitter and Receiver.

USB main features are:

·         Ser/Des is configured as USB 3.1.

·         Universal Serial Bus 3.1 (USB) subsystem with integrated USB2.0 PHY

·         Dual-Role Device (DRD) capability

·         Compliance with USB 3.1 Gen1 Specification

·         Support of Peripheral (aka Device) mode at Super Speed (SS at 5 Gbps), High Speed (HS at 480 Mbps), and Full Speed (FS at 12 Mbps)

·         Support of Host mode at Super Speed (SS at 5 Gbps), High Speed (HS at 480 Mbps), Full Speed (FS at 12 Mbps), and Low Speed (LS at 1.5 Mbps)

·         ECC on internal RAMs

UART

The AM64xx SOM can support up to 4 UART interfaces. The following figure describes the UART interfaces.

The UART interfaces main features are:

·         UART 0 supports TX, RX, CTS and RTS. After POR it is used as terminal.

·         UART 2 supports TX, RX, CTS and RTS.

·         UART 3 Supports TX, RX, CTS and RTS.

·         UART 4 support TX, RX

·         RS-485 external transceiver auto flow control support.

·         Baud rates up to 3.6 Mbps. Auto-baud between 1200 bits/s and 115.2 Kbits/s.

·         Flow control: Hardware (RTS/CTS) or software (XON/XOFF).

·         Optional multi-drop transmission.

eSPI

The AM64xx SOM supports two eSPI interface. The following figure describes the eSPI interface.

·         Single HW chip select nSS0.

·         Master/Slave configurable.

·         Serial clock with programmable frequency, polarity, and phase for each channel.

I2C

The AM64xx SOM supports up to two I2C Interfaces. The following figure describes the I2C interfaces.

The I2C main features are:

·         I2C-0 is connected to the SOM EEPROM and BtB connector.

·         I2C-1 is available on the connector by default.

·         Pull-up resistors assembled on SOM.

·         Multi-master operation.

·         In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.

·         In Fast mode, data transfer rates up to 400 kbits/s can be achieved.

uSD

The uSD supports the following features:

·         AM64xx’s MMC-1.

·        Optional on Carrier board

·        Implements 4 data bits.

·        SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01.

·        SDIO Specification v3.00

·        DDR50: UHS-I 1.8 V signalling, frequency up to 50 MHz, up to 50 MBps.

·        SDR104 is NOT supported.

·        Can be used as BOOT NVM *

MCAN

The AM64xx supports up to two CAN interfaces.

MCAN main features are:

·         Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015.

·         Full CAN FD support (up to 64 data bytes).

ADC

The AM64xx support up to eight Analog to Digital lines. The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1of 8 analog inputs (channels).

·         4 MSPS rate with a 60 MHz SMPL_CLK.

·         Functional Internal Diagnostic Debug Mode.

·         Single-ended or differential input options.

·         Simultaneous sampling is NOT supported.

GPIO

The AM64xx support GPIO interfaces that can be multiplex with alternative function interfaces. Some of the interfaces are:

·         Fast serial interface (FSI).

·         Enhanced Capture Module.

·         Enhanced PWM.

·         Timers

·         More

Connector’s Signal Description

J5001

J7

J9

Power & Reset

Power Architecture

The AM64xx SOM’s power is a single 5V source. It uses Discreet power converter to generate its power rails. The following figure describes the power architecture and power up sequencing.

The power architecture main features are:

·         Single 5V power source.

·         Buck-Boost on the input enable lower power connection e.g. battery.

·         3.3V output up to 1A (Need to calculate system and SOM power).

VPP_1V8

To program the CPU a power of 1.8V is required. To program the CPU, connect a 1.8V to J9-28. For normal operation leave this pin floating.

Reset

The AM64xx power is monitored by a voltage supervisor.

A reset can be triggered by an external reset signal (Switch) or the internal power fail. There is a pull-up on the SOM.

Power Consumption

power consumption table of the TI SOM:

Integration Manual

Power Up Sequence

The AM64xx is sourced by a single 5V input. All power sequences are supported by the PMIC.

When using the SOM 3.3V output there is no need to consider its power sequence. If an external power source is used, it needs to be power according to the power sequence rules. (See AM64xx datasheet for details)

Booting Options

Fuses Booting

Not Supported.

Booting from Resistors setting

The AM64xx SOM can boot from different NVM according to an external resistors configuration.

The available booting NVM are:

·         eMMC on MMC0.

·         uSD card on MMC1.

·         QSPI on QSPIA.

·         UART

·         USB

There are 16 boot mode signals [BOOTMODE 0-15]. The table below describes the supported boot option in the AM64xx system (SOM and Carrier).

I2C Interfaces

The AM64xx SOM uses I2C0 interface for its internal configurations. The following table describes the address mapping.

GPIO Interfaces

The AM64XX SoC uses some GPIO signals for its internal controls. The following table describes the GPIO allocation.

AM64xx Debugging Capability

The AM64XX SOM supports UART interface for debugging.

The UART interface is a null modem interface that is internally pulled up and support using SOC_MAIN_UART0_TX/RX signals.

he UART interface is optional to use and mentioned here since most of the software infrastructure used in HummingBoard Pulse uses it for debugging.

Mechanical Description

Following is a diagram of the TOP and BOTTOM view of the SR-AM64xx.

Note the following details:

·         The carrier board must use the same footprint as in the above mechanical footprint.
Since this is a TOP VIEW of the print side of the AM64xx, the diagram above describes the dimensions and placement of the board-to-board  headers, mechanical holes and boundaries of the AM64xx, as-is.

·         J9 is the main board-to-board  header (bottom side in the diagram).

·         J7 is the second board-to-board  header (upper side in the diagram).

·         J5001 is the third board-to-board  header (right side in the diagram).

·         In case 1.5mm mating height was chosen, then the AM64xx requirement would be that all area beneath it on the carrier will be all dedicated ONLY for the board-to-board connectivity; no other components are allowed.
In case higher mating is chosen, then 1.5mm should be reserved for the AM64xx. For instance, if 3.5mm mating height is chosen, then 1.5mm is dedicated to the AM64xx print side components and the remaining 2mm for the carrier components underneath the AM64xx.

Refer to SolidRun HummingBoard design and layout, where there are examples of the main and second 80 pin header board-to-board usage.

Documentation

Related Articles