CN9132 COM Hardware User Manual
Dual Revision and Notes
Date | Owner | Revision | Notes |
---|---|---|---|
Apr 26, 2020 | Alon Rotman | 1.0 |
|
Oct 10, 2020 | Alon Rotman | 1.1 |
|
Oct 29, 2020 | Alon Rotman | 1.2 | Updated CP[2:0] MPPs tables according to PCB rev1.1 |
Dec 01, 2024 | Josua Mayer | 1.3 | Cosmetic updates and minor corrections to MPP and connector tables according to PCB rev1.3 |
Dec 30, 2024 | Josua Mayer | 1.3.1 | Marked PTP feature as Untested. |
Table of Contents |
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Disclaimer
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.
Introduction
This document is intended for hardware engineers that are willing to integrate CN913x COM express type 7 module from SolidRun ltd.
The document provides details with regards CN913x module rev 1.3.
Overview
CN9132 COM Express type 7 is a highly integrated COM modules based on Marvell’s CN913x SoC.
The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 18 high speed SERDESs.
The module integrates the following features –
CN9130 SoC (up to 2.2GHz).
SO-DIMM DDR4 connected to the DDR controller. The SO-DIMM supports up to 16GByte SO-DIMM DDR4 2400Mtps memory with and without ECC, registered or non-registered.
Single 12V DC-input is required.
Specifications
Features | CN9132 | CN9131 | CN9130 |
---|---|---|---|
Form Factor | COM Express type 7 | COM Express type 7 | COM Express type 7 |
Processor Core | 4 cores Arm Cortex A72 | 4 cores Arm Cortex A72 | 4 cores Arm Cortex A72 |
Processor speed | Up to 2.2GHz | Up to 2.2GHz | Up to 2.2GHz |
Memory | Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel) | Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel) | Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel) |
ECC | Optional | Optional | Optional |
eMMC | Up to 64GB (assembled 8GB) | Up to 64GB (assembled 8GB) | Up to 64GB (assembled 8GB) |
Flash | 64Mbit SPI NOR flash | 64Mbit SPI NOR flash | 64Mbit SPI NOR flash |
SATA 3.0 | 2 | 1 | 0 |
Supported OS | Linux kernel 5.8x | Linux kernel 5.8x | Linux kernel 5.8x |
XFI/RXAUI/SGMII | 3 | 2 | 1 |
PCIe gen 3.0 | 1 x PCIe Gen 3.0 x4 | 1 x PCIe Gen 3.0 x4 | 1 x PCIe Gen 3.0 x4 |
USB 3.0 | 1 | 0 | 0 |
I2C | 6 | 5 | 4 |
SMI & XSMI | 3 | 2 | 1 |
UART | 2 | 2 | 2 |
PPS/PTP/Sync-E support | Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA). | Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA). | Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA). |
SPI bus | ✓ | ✓ | ✓ |
RTC support | ✓ | ✓ | ✓ |
Power | 12V (9V-15V) | 12V (9V-15V) | 12V (9V-15V) |
Environment | Commercial: 0°C to 70°C | Commercial: 0°C to 70°C | Commercial: 0°C to 70°C |
Dimensions | 125mm X 95mm | 125mm X 95mm | 125mm X 95mm |
Simplified Schematics
CN9130 COM express type 7 simplified schematics is intended for the following audience –
Software and firmware engineers that enables them to understand the IO and signal connectivity of the COM express design.
Hardware engineers that are willing to use the COM express and build their own development board. This document completes the CEx7 CN9130 reference manual from description of signal and implementation wise.
Power Consumption
TBD
High Speed port configuration
The CN9130 Com Express Type 7 family includes 3 variations:
CN9130 is comprised from a single CN9130.
CN9131 is comprised from a single CN9130 with one additional 88F8215. This includes a CP with 6 shared high speed SERDES interfaces, for a total of 12 lanes.
CN9132 is comprised from a single CN9130 with two additional 88F8215. Each one of them has a CP with 6 shared high speed SERDES interfaces, for a total of 18 lanes.
Maximum Port combination:
Feature | CN9132 | CN9131 | CN9130 |
---|---|---|---|
PCIe 3.0 | 1x Port X4 lanes | 1x Port X4 lanes | 1x Port X4 lanes |
Ethernet | 3x 10/5 GbE port + | 2x 10/5 GbE port + | 1x 10/5 GbE port + |
USB 3.0 | 6 x USB 3.0 | 4 x USB 3.0 | 2 x USB 3.0 |
SATA 3.0 | 6 x SATA 3.0 | 4 x SATA 3.0 | 2 x SATA 3.0 |
SERDES LANES | 18 Lanes | 12 Lanes | 6 Lanes |
88F8215 | 2 | 1 | 0 |
SERDES MUXing
Each CP (CP0, CP1 and CP2) support the same mux options individually:
Interface | SERDES Lane0 | SERDES Lane1 | SERDES Lane2 | SERDES Lane3 | SERDES Lane4 | SERDES Lane5 |
---|---|---|---|---|---|---|
10GBASE-R/XFI |
|
| Port 0 |
| Port 0 |
|
5GBASE-R |
|
| Port 0 |
| Port 0 or 1 |
|
10GBASE-X2 (RXAUI) |
|
| Port 0 Lane 0 | Port 0 Lane 1 | Port 0 Lane0 | Port 0 Lane 1 |
1000BASE-X (SGMII) / 2.5GBASE-X (HS-SGMII) | Port 1 | Port 2 | Port 0 | Port 1 | Port 0 or 1 | Port 2 |
SATA 3.0 | Port 1 | Port 0 | Port 0 | Port 1 |
| Port 1 |
USB 3.0 HOST |
| Port 0 | Port 0 | Port 1 | Port 1 |
|
USB 3.0 Device |
| Port 0 |
|
| Port0 |
|
PCIe | PCIex4 Port0 LANE0 | PCIex4 Port0 LANE1 | PCIex4 Port0 LANE2 | PCIex4 Port0 LANE3 | PCIex1 Port1 | PCIex1 Port2 |
Evaluation Board Default Configuration of CP0 | PCIex4 Port 0 Lane 0 | PCIex4 Port 0 Lane 1 | PCIex4 Port 0 Lane 2 | PCIex4 Port 0 Lane 3 | 10GBASE-R/XFI Port 0 | 2.5GBASE-X/HS-SGMII Port 2 |
Evaluation Board Default Configuration of CP1 | PCIex2 Port0 LANE0 | PCIex2 Port0 LANE1 | 10GBASE-R/XFI Port 0 | SATA 3.0 Port 1 | PCIex1 Port 1 | PCIex1 Port 2 |
Evaluation Board Default Configuration of CP2 | PCIex1 Port 0 | USB-3.0 Host Port 0 | 5GBASE-R/XFI Port 0 | SATA 3.0 Port 1 | PCIex1 Port 1 | PCIex1 Port 2 |
The following port configurations can’t be used simultaneously:
SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE
SGMII port 1 and HS SGMII port 1
SGMII port 2 and HS SGMII port 2
Note that all PCIe lanes specified in the CN9132 default configuration are connected to PCIe pins in the COM Express connector and are routed as 90 ohm differential pairs
AP/CP[0:2] Multi Purpose Pins
AP MPP[0:19]
MPP # | Pin # | Pin Description | Notes |
---|---|---|---|
AP_MPP[0] | AP10 | AP_SD_CLK | 1.8V, serial 22ohm resistor |
AP_MPP[1] | AT10 | AP_SD_CMD | 1.8V, 10K PU |
AP_MPP[2] | AP16 | AP_SD_D[0] | 1.8V, 10K PU |
AP_MPP[3] | AP18 | AP_SD_D[1] | 1.8V, 10K PU |
AP_MPP[4] | AT16 | AP_SD_D[2] | 1.8V, 10K PU |
AP_MPP[5] | AP14 | AP_SD_D[3] | 1.8V, 10K PU |
AP_MPP[6] | AP12 | AP_SD_DS | RCLK, 10K PD |
AP_MPP[7] | AT14 | AP_SD_D[4] | 1.8V, 10K PU |
AP_MPP[8] | AT12 | AP_SD_D[5] | 1.8V, 10K PU |
AP_MPP[9] | AT18 | AP_SD_D[6] | 1.8V, 10K PU |
AP_MPP[10] | AV18 | AP_SD_D[7] | 1.8V, 10K PU |
AP_MPP[11] | AY18 | AP_UA0_TXD | PD - Reset strap |
AP_MPP[12] | BA17 | AP_SD_HW_RST | 1.8V, 10K PD |
AP_MPP[19] | AW17 | AP_UA0_RXD | 3.3V through FXL2TD245L10X level shifter |
CP0 MPP[0:62]
MPP # | Pin # | Pin Description | Notes |
---|---|---|---|
MPP[0] | AY38 | CP_GE1_RXD[3] |
|
MPP[1] | AV38 | CP_GE1_RXD[2] |
|
MPP[2] | AW39 | CP_GE1_RXD[1] |
|
MPP[3] | AY40 | CP_GE1_RXD[0] |
|
MPP[4] | AW41 | CP_GE1_RXCTL |
|
MPP[5] | BA39 | CP_GE1_RXCLK |
|
MPP[6] | AW35 | CP_GE1_TXD[3] |
|
MPP[7] | AY36 | CP_GE1_TXD[2] |
|
MPP[8] | BA37 | CP_GE1_TXD[1] |
|
MPP[9] | AW37 | CP_GE1_TXD[0] |
|
MPP[10] | BA35 | CP_GE1_TXCTL |
|
MPP[11] | AV36 | CP_GE1_TXCLKOUT |
|
MPP[12] | AV32 | CP_SPI1_CSn[1] |
|
MPP[13] | AY34 | CP_SPI1_MISO | 3.3V |
MPP[14] | AT36 | CP_SPI1_CSn[0] | 3.3V, for on-SoM SPI Flash |
MPP[15] | AT32 | CP_SPI1_MOSI | 3.3V, 10k PD, CPU Subsystem Clock |
MPP[16] | AV34 | CP_SPI1_SCK | 3.3V, 10k PU, 1k PD via SW2-1, CPU Subsystem Clock |
MPP[17] | BA29 | CP_GPIO[17] | 3.3V, 10k PU, 1k PD via SW2-2, CPU Subsystem Clock |
MPP[18] | AW29 | CP_BOOT_MODE_SEL0 | 3.3V, 10k PU, 4.7k PD via SW1-5, Boot Mode[0] |
MPP[19] | AV30 | CP_BOOT_MODE_SEL1 | 3.3V, 10k PU, 4.7k PD via SW1-4, Boot Mode[1] |
MPP[20] | BA31 | CP_BOOT_MODE_SEL2 | 3.3V, 10k PU, 4.7k PD via SW1-3, Boot Mode[2] |
MPP[21] | AT30 | CP_BOOT_MODE_SEL3 | 3.3V, 10k PU, 1k PD via SW1-2, Boot Mode[3] |
MPP[22] | AY30 |
SolidRun Ltd.