CN9132 COM Hardware User Manual

Dual Revision and Notes

Date	Owner	Revision	Notes

Date	Owner	Revision	Notes
Apr 26, 2020	Alon Rotman	1.0	Initial release information Relevant for PCB revision 1.0
Oct 10, 2020	Alon Rotman	1.1	Update CN913x configurations Update Connector A/B C/D pinout Relevant for PCB rev1.1
Oct 29, 2020	Alon Rotman	1.2	Updated CP[2:0] MPPs tables according to PCB rev1.1
Dec 01, 2024	Josua Mayer	1.3	Cosmetic updates and minor corrections to MPP and connector tables according to PCB rev1.3
Table of Contents	1 Dual Revision and Notes 2 Introduction 2.1 Overview 2.2 Specifications 3 Simplified Schematics 4 Power Consumption 5 High Speed port configuration 5.1 Maximum Port combination: 6 SERDES MUXing 6.1 Each CP (CP0, CP1 and CP2) support the same mux options individually: 7 AP/CP[0:2] Multi Purpose Pins 7.1 AP MPP[0:19] 7.2 CP0 MPP[0:62] 7.3 CP1 MPP[0:62] 7.4 CP2 MPP[0:62] 8 Assembly Options 8.1 CP0 SDIO Interface Voltage Domain 8.2 CP2 GE1 (RGMII) Interface Voltage Domain 8.3 Trusted Platform Module 8.4 SMB_ALERT_N 8.5 BIOS_DIS0# / BIOS_DIS1# 9 COM Express Header Details 9.1 AB Header 9.2 CD Header 10 Common Questions and Answers 11 Documentation 12 Related Articles

Disclaimer

No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

Introduction

This document is intended for hardware engineers that are willing to integrate CN913x COM express type 7 module from SolidRun ltd.

The document provides details with regards CN913x module rev 1.3.

Overview

CN9132 COM Express type 7 is a highly integrated COM modules based on Marvell’s CN913x SoC.
The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 18 high speed SERDESs.

The module integrates the following features –

CN9130 SoC (up to 2.2GHz).
SO-DIMM DDR4 connected to the DDR controller. The SO-DIMM supports up to 16GByte SO-DIMM DDR4 2400Mtps memory with and without ECC, registered or non-registered.
Single 12V DC-input is required.

Specifications

Features	CN9132	CN9131	CN9130

Features	CN9132	CN9131	CN9130
Form Factor	COM Express type 7	COM Express type 7	COM Express type 7
Processor Core	4 cores Arm Cortex A72	4 cores Arm Cortex A72	4 cores Arm Cortex A72
Processor speed	Up to 2.2GHz	Up to 2.2GHz	Up to 2.2GHz
Memory	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)	Dual Channel SO-DIMM DDR4; up to 32GB at 2400MT/s (16GB for each channel)
ECC	Optional	Optional	Optional
eMMC	Up to 64GB (assembled 8GB)	Up to 64GB (assembled 8GB)	Up to 64GB (assembled 8GB)
Flash	64Mbit SPI NOR flash	64Mbit SPI NOR flash	64Mbit SPI NOR flash
SATA 3.0	2	1	0
Supported OS	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node	Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node
XFI/RXAUI/SGMII	3	2	1
PCIe gen 3.0	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x2 6 x PCIe Gen 3.0 x1	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x2 3 x PCIe Gen 3.0 x1	1 x PCIe Gen 3.0 x4 1 x PCIe Gen 3.0 x1
USB 3.0	1	0	0
I2C	6	5	4
SMI & XSMI	3	2	1
UART	2	2	2
PPS/PTP support	✓	✓	✓
SPI bus	✓	✓	✓
RTC support	✓	✓	✓
Power	12V (9V-15V) up to 15W full system	12V (9V-15V) up to 13W full system	12V (9V-15V) up to 11W full system
Environment	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%	Commercial: 0°C to 70°C Industrial: -40°C to 85°C Humidity (non-condensing): 10% – 90%
Dimensions	125mm X 95mm	125mm X 95mm	125mm X 95mm

Simplified Schematics

CN9130 COM express type 7 simplified schematics is intended for the following audience –

Software and firmware engineers that enables them to understand the IO and signal connectivity of the COM express design.
Hardware engineers that are willing to use the COM express and build their own development board. This document completes the CEx7 CN9130 reference manual from description of signal and implementation wise.

Power Consumption

TBD

High Speed port configuration

The CN9130 Com Express Type 7 family includes 3 variations:

CN9130 is comprised from a single CN9130.
CN9131 is comprised from a single CN9130 with one additional 88F8215. This includes a CP with 6 shared high speed SERDES interfaces, for a total of 12 lanes.
CN9132 is comprised from a single CN9130 with two additional 88F8215. Each one of them has a CP with 6 shared high speed SERDES interfaces, for a total of 18 lanes.

Maximum Port combination:

Feature	CN9132	CN9131	CN9130

Feature	CN9132	CN9131	CN9130
PCIe 3.0	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes	1x Port X4 lanes + 2x Ports X1 Total of 3 controllers and up to 6 lanes
Ethernet	3x 10/5 GbE port + 6x 1/2.5 GbE Ports or 6x 5 GbE Port + 3x 1/2.5 GbE Port	2x 10/5 GbE port + 4x 1/2.5 GbE Ports or 4x 5 GbE Port + 2x 1/2.5 GbE Port	1x 10/5 GbE port + 2x 1/2.5 GbE Ports or 2x 5 GbE Port + 1x 1/2.5 GbE Port
USB 3.0	6 x USB 3.0 (Host/Device)	4 x USB 3.0 (Host/Device)	2 x USB 3.0 (Host/Device)
SATA 3.0	6 x SATA 3.0	4 x SATA 3.0	2 x SATA 3.0
SERDES LANES	18 Lanes	12 Lanes	6 Lanes
88F8215	2	1	0

SERDES MUXing

Each CP (CP0, CP1 and CP2) support the same mux options individually:

Interface	SERDES Lane0	SERDES Lane1	SERDES Lane2	SERDES Lane3	SERDES Lane4	SERDES Lane5

Interface	SERDES Lane0	SERDES Lane1	SERDES Lane2	SERDES Lane3	SERDES Lane4	SERDES Lane5
10GBASE-R/XFI			Port 0		Port 0
5GBASE-R			Port 0		Port 0 or 1
10GBASE-X2 (RXAUI)			Port 0 Lane 0	Port 0 Lane 1	Port 0 Lane0	Port 0 Lane 1
1000BASE-X (SGMII) / 2.5GBASE-X (HS-SGMII)	Port 1	Port 2	Port 0	Port 1	Port 0 or 1	Port 2
SATA 3.0	Port 1	Port 0	Port 0	Port 1		Port 1
USB 3.0 HOST		Port 0	Port 0	Port 1	Port 1
USB 3.0 Device		Port 0			Port0
PCIe RC/EP	PCIex4 Port0 LANE0	PCIex4 Port0 LANE1	PCIex4 Port0 LANE2	PCIex4 Port0 LANE3	PCIex1 Port1	PCIex1 Port2
Evaluation Board Default Configuration of CP0	PCIex4 Port 0 Lane 0	PCIex4 Port 0 Lane 1	PCIex4 Port 0 Lane 2	PCIex4 Port 0 Lane 3	10GBASE-R/XFI Port 0	2.5GBASE-X/HS-SGMII Port 2
Evaluation Board Default Configuration of CP1	PCIex2 Port0 LANE0	PCIex2 Port0 LANE1	10GBASE-R/XFI Port 0	SATA 3.0 Port 1	PCIex1 Port 1	PCIex1 Port 2
Evaluation Board Default Configuration of CP2	PCIex1 Port 0	USB-3.0 Host Port 0	5GBASE-R/XFI Port 0	SATA 3.0 Port 1	PCIex1 Port 1	PCIex1 Port 2

The following port configurations can’t be used simultaneously:

SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE
SGMII port 1 and HS SGMII port 1
SGMII port 2 and HS SGMII port 2

Note that all PCIe lanes specified in the CN9132 default configuration are connected to PCIe pins in the COM Express connector and are routed as 90 ohm differential pairs

AP/CP[0:2] Multi Purpose Pins

AP MPP[0:19]

MPP #	Pin #	Pin Description	Notes

MPP #	Pin #	Pin Description	Notes
AP_MPP[0]	AP10	AP_SD_CLK	1.8V, serial 22ohm resistor
AP_MPP[1]	AT10	AP_SD_CMD	1.8V, 10K PU
AP_MPP[2]	AP16	AP_SD_D[0]	1.8V, 10K PU
AP_MPP[3]	AP18	AP_SD_D[1]	1.8V, 10K PU
AP_MPP[4]	AT16	AP_SD_D[2]	1.8V, 10K PU
AP_MPP[5]	AP14	AP_SD_D[3]	1.8V, 10K PU
AP_MPP[6]	AP12	AP_SD_DS	RCLK, 10K PD
AP_MPP[7]	AT14	AP_SD_D[4]	1.8V, 10K PU
AP_MPP[8]	AT12	AP_SD_D[5]	1.8V, 10K PU
AP_MPP[9]	AT18	AP_SD_D[6]	1.8V, 10K PU
AP_MPP[10]	AV18	AP_SD_D[7]	1.8V, 10K PU
AP_MPP[11]	AY18	AP_UA0_TXD	PD - Reset strap 3.3V through FXL2TD245L10X level shifter
AP_MPP[12]	BA17	AP_SD_HW_RST	1.8V, 10K PD
AP_MPP[19]	AW17	AP_UA0_RXD	3.3V through FXL2TD245L10X level shifter

CP0 MPP[0:62]

MPP #	Pin #	Pin Description	Notes

MPP #	Pin #	Pin Description	Notes
MPP[0]	AY38	CP_GE1_RXD[3]
MPP[1]	AV38	CP_GE1_RXD[2]
MPP[2]	AW39	CP_GE1_RXD[1]
MPP[3]	AY40	CP_GE1_RXD[0]
MPP[4]	AW41	CP_GE1_RXCTL
MPP[5]	BA39	CP_GE1_RXCLK
MPP[6]	AW35	CP_GE1_TXD[3]
MPP[7]	AY36	CP_GE1_TXD[2]
MPP[8]	BA37	CP_GE1_TXD[1]
MPP[9]	AW37	CP_GE1_TXD[0]
MPP[10]	BA35	CP_GE1_TXCTL
MPP[11]	AV36	CP_GE1_TXCLKOUT
MPP[12]	AV32	CP_SPI1_CSn[1]	3.3V
MPP[13]	AY34	CP_SPI1_MISO	3.3V
MPP[14]	AT36	CP_SPI1_CSn[0]	3.3V, for on-SoM SPI Flash
MPP[15]	AT32	CP_SPI1_MOSI	3.3V, 10k PD, CPU Subsystem Clock CP0_SYS_PLL_SEL0
MPP[16]	AV34	CP_SPI1_SCK	3.3V, 10k PU, 1k PD via SW2-1, CPU Subsystem Clock CP0_SYS_PLL_SEL1
MPP[17]	BA29	CP_GPIO[17]	3.3V, 10k PU, 1k PD via SW2-2, CPU Subsystem Clock CP0_SYS_PLL_SEL2
MPP[18]	AW29	CP_BOOT_MODE_SEL0	3.3V, 10k PU, 4.7k PD via SW1-5, Boot Mode[0]
MPP[19]	AV30	CP_BOOT_MODE_SEL1	3.3V, 10k PU, 4.7k PD via SW1-4, Boot Mode[1]
MPP[20]	BA31	CP_BOOT_MODE_SEL2	3.3V, 10k PU, 4.7k PD via SW1-3, Boot Mode[2]
MPP[21]	AT30	CP_BOOT_MODE_SEL3	3.3V, 10k PU, 1k PD via SW1-2, Boot Mode[3]
MPP[22]	AY30	CP_BOOT_MODE_SEL4	3.3V, 10k PU, 4.7k PD via SW1-1, Boot Mode[4]
MPP[23]	AP32	CP_BOOT_MODE_SEL5	3.3V, 10k PU, Boot Mode[5]
MPP[24]	AP34	CP_MPP[24]	3.3V, 2.2K PU
MPP[25]	AT34	CP_MPP[25]	3.3V, 2.2k PD, Reset strap
MPP[26]	AT38	CP_MPP[26]	3.3V, 10k PU, Reset strap
MPP[27]	AW31	CP_MPP[27]	3.3V, 10K PU, SODIMM EVENT_N
MPP[28]	AY32	CP_PTP_PULSE
MPP[29]	BA33	CP_PTP_CLK
MPP[30]	AW33	CP_PTP_PCLK_OUT
MPP[31]	AP36	CP_MPP[31]	3.3V, 2.2K PU, PWRBTN_N
MPP[32]	H30	CP_MPP[32]	BIOS_DIS status
MPP[33]	C39	CP_MPP[33]	BIOS_DIS override BIOS_DIS
MPP[34]	C41	CP_MPP[34]	3.3V, 2.2K PU, SUS_5_N
MPP[35]	F32	CP_I2C1_SDA	3.3V, 2.2K PU, i2c mux, used addresses: 0x53, 0x2F, 0x6A, 0x51
MPP[36]	H32	CP_I2C1_SCK	3.3V, 2.2K PU
MPP[37]	F34	CP_I2C0_SCK	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[38]	H34	CP_I2C0_SDA	3.3V, 2.2K PU EEPROM 0x50, SPD 0x53
MPP[39]	F30	CP_MPP[39]	FAN_PWM_R
MPP[40]	F36	CP_SMI_MDIO	3.3V, 2.2K PU
MPP[41]	H36	CP_SMI_MDC	3.3V, 2.2K PU
MPP[42]	E39	CP_XSMI_MDC	3.3V, 2.2K PU, can replace CP_SMI_MDC by assembly option
MPP[43]	D30	CP_XSMI_MDIO	3.3V, 2.2K PU, can replace CP_SMI_MDIO by assembly option
MPP[44]	D38	CP_MPP[44]	3.3V, 10k PD, PCIe0 clock config
MPP[45]	A39	CP_MPP[45]	3.3V, 10k PD, Reset strap
MPP[46]	C37	CP_MPP[46]	3.3V, 10k PD, CPU Subsystem Clock CP0_SYS_PLL_SEL3
MPP[47]	A37	CP_MPP[47]	3.3V, 2.2k PD, Reset strap
MPP[48]	B40	CP_MPP[48]	3.3V, 10k PD, PCIe1 clock config
MPP[49]	B38	CP_MPP[49]	3.3V, 1k PD, can enable 1.8V supply for CP0:CP_VHV
MPP[50]	C35	CP_UA2_TXD	3.3V
MPP[51]	D34	CP_UA2_RXD	3.3V
MPP[52]	A35	CP_RCVR1_CLK/CP_RCVR2_CLK	3.3V, Recovered clock for SyncE
MPP[53]	B36	AP_VHV_EN	3.3V, 1k PD, can enable 1.8V supply for AP_VHV
MPP[54]	D36	CP_MPP[54]	3.3V, connected with ethernet phy clock output
MPP[55]	B34	CP_SD_CRD_DT	3.3V, 2.2k PU
MPP[56]	D32	CP_SD_CLK	3.3V (1.8V assembly option)
MPP[57]	B32	CP_SD_CMD	3.3V (1.8V assembly option)
MPP[58]	A33	CP_SD_D[0]	3.3V (1.8V assembly option)
MPP[59]	C33	CP_SD_D[1]	3.3V (1.8V assembly option)
MPP[60]	A31	CP_SD_D[2]	3.3V (1.8V assembly option)
MPP[61]	C31	CP_SD_D[3]	3.3V (1.8V assembly option)
MPP[62]	B30	NC	3.3V (1.8V assembly option)

CP1 MPP[0:62]

MPP #	Pin #	Pin Description	Notes

MPP #	Pin #	Pin Description	Notes
MPP[0]	AB21	NC	3.3V
MPP[1]	AC21	NC	3.3V
MPP[2]	AA22	NC	3.3V
MPP[3]	AA23	NC	3.3V
MPP[4]	AA21	NC	3.3V
MPP[5]	AB22	NC	3.3V
MPP[6]	AC18	NC	3.3V
MPP[7]	AB18	NC	3.3V
MPP[8]	AA19	NC	3.3V
MPP[9]	AA20	NC	3.3V
MPP[10]	AA18	NC	3.3V
MPP[11]	AB19	CP_MPP[11]	3.3V, BATLOW_N
MPP[12]	AA12	CP_MPP[12]	3.3V, SPKR
MPP[13]	AB13	CP_SPI1_MISO	3.3V, 2.2k PU
MPP[14]	AA17	CP_SPI1_CSn[0]	3.3V, 2.2k PU, for on-SoM TPM (assembly option)
MPP[15]	AA14	CP_SPI1_MOSI	3.3V, 10k PD
MPP[16]	AA13	CP_SPI1_SCK	3.3V, 10k PU
MPP[17]	AA8	CP_MPP[17]	3.3V, 2.2k PU, TPM PIRQ_N
MPP[18]	AA9	CP_MPP[18]	3.3V, Boot Mode[0]
MPP[19]	AB9	CP_MPP[19]	3.3V, Boot Mode[1]
MPP[20]	AB10	CP_MPP[20]	3.3V, Boot Mode[2]
MPP[21]	AA7	CP_MPP[21]	3.3V, Boot Mode[3]
MPP[22]	AC9	CP_MPP[22]	3.3V, Boot Mode[4]
MPP[23]	AB16	CP_MPP[23]	3.3V, Boot Mode[5]
MPP[24]	AA16	NC	3.3V
MPP[25]	AB15	CP_MPP[25]	3.3V, 2.2k PD, Reset strap
MPP[26]	AC15	CP_MPP[26]	3.3V, 2.2k PD, Reset strap
MPP[27]	AA10	NC	3.3V
MPP[28]	AA11	CP_PTP_PULSE	3.3V
MPP[29]	AC12	CP_PTP_CLK	3.3V
MPP[30]	AB12	CP_PTP_PCLK_OUT	3.3V
MPP[31]	AA15	NC	3.3V
MPP[32]	A9	NC	3.3V
MPP[33]	B5	CP_MPP[33]	3.3V, THERMTRIP_N
MPP[34]	B6	CP_MPP[34]	3.3V, THRM_N
MPP[35]	C11	CP_I2C1_SDA	3.3V, 2.2k PU
MPP[36]	C10	CP_I2C1_SCK	3.3V, 2.2k PU
MPP[37]	C9	CP_XSMI_MDC	3.3V, 2.2k PU
MPP[38]	B9	CP_XSMI_MDIO	3.3V, 2.2k PU
MPP[39]	C8	CP_SATA1_PRESENT_ACTIVEn	3.3V
MPP[40]	C7	CP_MPP[4]	3.3V, WAKE0
MPP[41]	C8	NC	3.3V
MPP[42]	A6	CP_MPP[42]	3.3V, 2.2k PU, 10G_PHY_RST_23
MPP[43]	C6	CP_MPP[43]	3.3V, 2.2k PU, 10G_PHY_RST_01
MPP[44]	B3	CP_MPP[44]	3.3V, 10k PD, PCIe0 clock config
MPP[45]	C4	NC	3.3V, 10k PD, Reset strap
MPP[46]	B2	NC	3.3V
MPP[47]	C2	NC	3.3V, 2.2k PD, Reset strap
MPP[48]	C5	NC	3.3V, PCIe1 clock config
MPP[49]	A3	NC	3.3V
MPP[50]	D3	CP_MPP[50]	3.3V, 2.2K PU, CP1_SFP_INT1
MPP[51]	E2	CP_MPP[51]	3.3V, 2.2K PU, WAKE1
MPP[52]	E3	CP_RCVR1_CLK/CP_RCVR2_CLK	3.3V, Recovered clock for SyncE
MPP[53]	C3	NC	3.3V
MPP[54]	C1	NC	3.3V
MPP[55]	F2	NC	3.3V
MPP[56]	H3	NC	3.3V
MPP[57]	H2	NC	3.3V
MPP[58]	G3	NC	3.3V
MPP[59]	F3	NC	3.3V
MPP[60]	J1	NC	3.3V
MPP[61]	J2	NC	3.3V
MPP[62]	F1	NC	3.3V

CP2 MPP[0:62]

MPP #	Pin #	Pin Description	Notes

MPP #	Pin #	Pin Description	Notes
MPP[0]	AB21	CP_UA0_RXD	3.3V (1.8V assembly option), RSVD0
MPP[1]	AC21	CP_UA0_TXD	3.3V (1.8V assembly option), RSVD1
MPP[2]	AA22	CP_UA1_RXD	3.3V (1.8V assembly option), RSVD2
MPP[3]	AA23	CP_UA1_TXD	3.3V (1.8V assembly option), RSVD3
MPP[4]	AA21	CP_UA1_CTS	3.3V (1.8V assembly option), RSVD4
MPP[5]	AB22	CP_UA1_RTS	3.3V (1.8V assembly option), RSVD5
MPP[6]	AC18	CP_SATA1_PRESENTn	3.3V (1.8V assembly option), RSVD6
MPP[7]	AB18	CP_SPI0_CSn[1]	3.3V (1.8V assembly option), RSVD7
MPP[8]	AA19	CP_SPI0_CSn[0]	3.3V (1.8V assembly option), RSVD8
MPP[9]	AA20	CP_SPI0_MOSI	3.3V (1.8V assembly option), RSVD9
MPP[10]	AA18	CP_SPI0_MISO	3.3V (1.8V assembly option), RSVD10
MPP[11]	AB19	CP_SPI0_SCK	3.3V (1.8V assembly option), RSVD11
MPP[12]	AA12	NC	3.3V
MPP[13]	AB13	NC	3.3V
MPP[14]	AA17	NC	3.3V
MPP[15]	AA14	NC	3.3V
MPP[16]	AA13	NC	3.3V
MPP[17]	AA8	NC	3.3V
MPP[18]	AA9	CP0_BOOT_MODE_SEL0	3.3V
MPP[19]	AB9	CP0_BOOT_MODE_SEL1	3.3V
MPP[20]	AB10	CP0_BOOT_MODE_SEL2	3.3V
MPP[21]	AA7	CP0_BOOT_MODE_SEL3	3.3V
MPP[22]	AC9	CP0_BOOT_MODE_SEL4	3.3V
MPP[23]	AB16	CP0_BOOT_MODE_SEL5	3.3V
MPP[24]	AA16	NC	3.3V
MPP[25]	AB15	CP_MPP[25]	3.3V, 2.2k PD, Reset strap
MPP[26]	AC15	CP_MPP[26]	3.3V, 2.2k PD, Reset strap
MPP[27]	AA10	CP_MPP[27]	3.3V, RSVD27
MPP[28]	AA11	CP2_PTP_PULSE	3.3V
MPP[29]	AC12	CP2_PTP_CLK_IN	3.3V
MPP[30]	AB12	CP2_PTP_PCLK_OUT	3.3V
MPP[31]	AA15	CP_MPP[31]	3.3V, RSVD31
MPP[32]	A9	CP_MPP[32]	3.3V, RSVD32
MPP[33]	B5	NC	3.3V
MPP[34]	B6	NC	3.3V
MPP[35]	C11	CP_I2C1_SDA	3.3V, 2.2k PU
MPP[36]	C10	CP_I2C1_SCK	3.3V, 2.2k PU
MPP[37]	C9	CP_SMI_MDC/CP_XSMI_MDC	3.3V, 2.2K PU
MPP[38]	B9	CP_SMI_MDIO/CP_XSMI_MDIO	3.3V, 2.2K PU
MPP[39]	C8	NC	3.3V
MPP[40]	C7	CP_MPP[40]	3.3V, GPO2
MPP[41]	C8	NC	3.3V
MPP[42]	A6	CP_MPP[42]	3.3V, 2.2k PU, RSVD37
MPP[43]	C6	CP_MPP[43]	3.3V, 2.2k PU, RSVD38
MPP[44]	B3	CP_MPP[44]	3.3V, 10k PD, PCIe0 clock config
MPP[45]	C4	NC	3.3V, 10k PD, Reset strap
MPP[46]	B2	NC	3.3V
MPP[47]	C2	NC	3.3V, 2.2k PD, Reset strap
MPP[48]	C5	NC	3.3V, PCIe1 clock config
MPP[49]	A3	NC	3.3V
MPP[50]	D3	CP_MPP[50]	3.3V, 2.2k PU, CP2_SFP_INT2
MPP[51]	E2	NC	3.3V
MPP[52]	E3	NC	3.3V
MPP[53]	C3	NC	3.3V
MPP[54]	C1	NC	3.3V
MPP[55]	F2	CP_MPP[55]	3.3V, RSVD55
MPP[56]	H3	CP_MPP[56]	3.3V, RSVD56
MPP[57]	H2	NC	3.3V
MPP[58]	G3	NC	3.3V
MPP[59]	F3	NC	3.3V
MPP[60]	J1	NC	3.3V
MPP[61]	J2	NC	3.3V
MPP[62]	F1	NC	3.3V

Assembly Options

Under MOQ certain customizations are possible by special assembly. This is an incomplete list of such options:

CP0 SDIO Interface Voltage Domain

CP0 Signals MPP[56:62] are by default configured for 3.3V signalling. They can be switched to 1.8V by removing R349 and adding R348.

CP2 GE1 (RGMII) Interface Voltage Domain

CP2 Signals MPP[0:11] are by default configured for 3.3V signalling. They can be switched to 1.8V by removing R543 and adding R544.

Trusted Platform Module

The module can accomodate a TPM (SLB9670 at U15). By default modules ship without.

SMB_ALERT_N

This signal can optionally be driven by CP0 MPP[23] (CP0_BOOT_MODE_SEL5) when assembling R536. By default it is not connected.

BIOS_DIS0# / BIOS_DIS1#

By default BIOS_DIS0# controls a mux that can swap SPI CS0 (for SPI Flash on COM) and CS1 (routed to carrier) used during boot. BIOS_DIS1# is floating by default.

Optionally BIOS_DIS1# may control the mux if R264 is assembled, BIOS_DIS0# may be disconnected by removing R263.

COM Express Header Details

Following are the COM express type 7 AB and CD pin mapping –

Pins marked with strikethrough are unused / unconnected pins
Pins marked with Red are GND or power

AB Header

Notes	Driving IC	Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes

Notes	Driving IC	Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
		GND (FIXED)	A1	B1	GND (FIXED)
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI3-	A2	B2	GBE0_ACT#	88E1512 PHY LED[1]
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI3+	A3	B3	LPC_FRAME#		Not used
Not used		GBE0_LINK100#	A4	B4	LPC_AD0		Not used
	88E1512 PHY LED[2]	GBE0_LINK1000#	A5	B5	LPC_AD1		Not used
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI2-	A6	B6	LPC_AD2		Not used
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI2+	A7	B7	LPC_AD3		Not used
	88E1512 PHY LED[0]	GBE0_LINK#	A8	B8	LPC_DRQ0#		Not used
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI1-	A9	B9	LPC_DRQ1#		Not used
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI1+	A10	B10	LPC_CLK		Not used
		GND (FIXED)	A11	B11	GND (FIXED)
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI0-	A12	B12	PWRBTN#	CP0 MPP[31]	3.3V, 2.2k PU
	CP0 Port 0 (RGMII) via 88E1512 PHY	GBE0_MDI0+	A13	B13	SMB_CK	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 3	3.3V, 2.2k pull-up
Not used		GBE0_CTREF	A14	B14	SMB_DAT	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 3	3.3V, 2.2k pull-up
Not used		SUS_S3#	A15	B15	SMB_ALERT#	CP0 MPP[23]	3.3V, 10k PU, assembly option
Serial 10nF	CP1 SD[3]	SATA0_TX+	A16	B16	SATA1_TX+	CP2 SD[3]	Serial 10nF
Serial 10nF	CP1 SD[3]	SATA0_TX-	A17	B17	SATA1_TX-	CP2 SD[3]	Serial 10nF
Not used		SUS_S4#	A18	B18	SUS_STAT#
Serial 10nF	CP1 SD[3]	SATA0_RX+	A19	B19	SATA1_RX+	CP2 SD[3]	Serial 10nF
Serial 10nF	CP1 SD[3]	SATA0_RX-	A20	B20	SATA1_RX-	CP2 SD[3]	Serial 10nF
		GND (FIXED)	A21	B21	GND (FIXED)
Not used		PCIE_TX15+	A22	B22	PCIE_RX15+		Not used
Not used		PCIE_TX15-	A23	B23	PCIE_RX15-		Not used
3.3v, 2.2k pull-up	CP0 MPP[34]	SUS_S5#	A24	B24	PWR_OK	Power enable	3.3V, 4.7k PU, Refer to power-up sequence
Not used		PCIE_TX14+	A25	B25	PCIE_RX14+		Not used
Not used		PCIE_TX14-	A26	B26	PCIE_RX14+		Not used
3.3V	CP1 MPP[11]	BATLOW#	A27	B27	WDT		Not used
3.3V	CP1 MPP[39]	SATA_ACT#	A28	B28	RSVD	CP2 MPP[8]	RSVD8 1.8V / 3.3V
RSVD0 1.8V / 3.3V	CP2 MPP[0]	RSVD	A29	B29	RSVD	CP2 MPP[9]	RSVD9 1.8V / 3.3V
RSVD1 1.8V / 3.3V	CP2 MPP[1]	RSVD	A30	B30	RSVD	CP2 MPP[10]	RSVD10 1.8V / 3.3V
		GND (FIXED)	A31	B31	GND (FIXED)
RSVD2 1.8V / 3.3V	CP2 MPP[2]	RSVD	A32	B32	SPKR	CP1 MPP[12]	3.3V
RSVD3 1.8V / 3.3V	CP2:CP_MPP[3]	RSVD	A33	B33	I2C_CK	CP0 MPP[36]	CP0 I2C1, shared with I2C Mux @ 0x77
3.3v, 2.2k pull-up	SPI CS0/1 switch	BIOS_DIS0#	A34	B34	I2C_DAT	CP0 MPP[35]	CP0 I2C1, shared with I2C Mux @ 0x77
3.3V	CP1 MPP[33]	THRMTRIP#	A35	B35	THRM#	CP1 MPP[34]
Not used		PCIE_TX13+	A36	B36	PCIE_RX13+		Not used
Not used		PCIE_TX13-	A37	B37	PCIE_RX13-		Not used
		GND	A38	B38	GND
Serial 220nF	CP1 SD[4]	PCIE_TX12+	A39	B39	PCIE_RX12+	CP1 SD[4]
Serial 220nF	CP1 SD[4]	PCIE_TX12-	A40	B40	PCIE_RX12+	CP1 SD[4]
		GND (FIXED)	A41	B41	GND (FIXED)
	CP1 USB-2.0 PHY 0	USB2-	A42	B42	USB3-	CP0 USB-2.0 PHY 1
	CP1 USB-2.0 PHY 0	USB2+	A43	B43	USB3+	CP0 USB-2.0 PHY 1
Not used		USB_2_3_OC#	A44	B44	USB_0_1_OC#
	CP0 USB-2.0 PHY 0	USB0-	A45	B45	USB1-	CP2 USB-2.0 PHY 0
	CP0 USB-2.0 PHY 0	USB0+	A46	B46	USB1+	CP2 USB-2.0 PHY 0
3.3V, 100nF, assembly option for diode sharing 3.3V supply	CP0 RTC	VCC_RTC	A47	B47	ESPI_EN		Not used
RSVD4 1.8V / 3.3V	CP2 MPP[4]	RSVD	A48	B48	RSVD	CP2 MPP[11]	RSVD11 1.8V / 3.3V
PTP_CP1_CLK_IN	CP1 MPP[29]	RSVD	A49	B49	SYS_RESET#	System Reset input	3.3V, 10k PU
Not used		LPC_SERIRQ	A50	B50	CB_RESET#	Carrier board reset output, can be used as PERST	3.3V, full drive
		GND (FIXED)	A51	B51	GND (FIXED)
Serial 220nF	CP1 SD[1]	PCIE_TX5+	A52	B52	PCIE_RX5+	CP1 SD[1]
Serial 220nF	CP1 SD[1]	PCIE_TX5-	A53	B53	PCIE_RX5-	CP1 SD[1]
microSD D[0]	CP0 MPP[58]	GPI0	A54	B54	GPO1	CP0 MPP[57]	microSD CMD
Serial 220nF	CP1 SD[0]	PCIE_TX4+	A55	B55	PCIE_RX4+	CP1 SD[0]
Serial 220nF	CP1 SD[0]	PCIE_TX4-	A56	B56	PCIE_RX4-	CP1 SD[0]
		GND	A57	B57	GPO2	CP2 MPP[40]	3.3V
Serial 220nF	CP0 SD[3]	PCIE_TX3+	A58	B58	PCIE_RX3+	CP0 SD[3]
Serial 220nF	CP0 SD[3]	PCIE_TX3-	A59	B59	PCIE_RX3-	CP0 SD[3]
		GND (FIXED)	A60	B60	GND (FIXED)
Serial 220nF	CP0 SD[2]	PCIE_TX2+	A61	B61	PCIE_RX2+	CP0 SD[2]
Serial 220nF	CP0 SD[2]	PCIE_TX2-	A62	B62	PCIE_RX2-	CP0 SD[2]
microSD D[1]	CP0 MPP[59]	GPI1	A63	B63	GPO3/SD_CD	CP0 MPP[55]	micro SD CD
Serial 220nF	CP0 SD[1]	PCIE_TX1+	A64	B64	PCIE_RX1+	CP0 SD[1]
Serial 220nF	CP0 SD[1]	PCIE_TX1-	A65	B65	PCIE_RX1-	CP0 SD[1]
		GND	A66	B66	WAKE0#	CP1 MPP[40]	3.3V, 2.2k PU
microSD D[2]	CP0 MPP[60]	GPI2	A67	B67	WAKE1#	CP1 MPP[51]	3.3V, 2.2k PU
Serial 220nF	CP0 SD[0]	PCIE_TX0+	A68	B68	PCIE_RX0+	CP0 SD[0]
Serial 220nF	CP0 SD[0]	PCIE_TX0-	A69	B69	PCIE_RX0-	CP0 SD[0]
		GND (FIXED)	A70	B70	GND (FIXED)
Serial 220nF	CP0 SD[5]	PCIE_TX8+	A71	B71	PCIE_RX8+	CP0 SD[5]
Serial 220nF	CP0 SD[5]	PCIE_TX8-	A72	B72	PCIE_RX8-	CP0 SD[5]
		GND	A73	B73	GND
Not used		PCIE_TX9+	A74	B74	PCIE_RX9+		Not used
Not used		PCIE_TX9-	A75	B75	PCIE_RX9-		Not used
		GND	A76	B76	GND
Not used		PCIE_TX10+	A77	B77	PCIE_RX10+		Not used
Not used		PCIE_TX10-	A78	B78	PCIE_RX10-		Not used
		GND	A79	B79	GND
		GND (FIXED)	A80	B80	GND (FIXED)
Not used		PCIE_TX11+	A81	B81	PCIE_RX11+		Not used
Not used		PCIE_TX11-	A82	B82	PCIE_RX11-		Not used
		GND	A83	B83	GND
Not used		NCSI_TX_EN	A84	B84	VCC_5V_SBY		Not used
microSD D[3]	CP0 MPP[61]	GPI3	A85	B85	VCC_5V_SBY		Not used
RSVD5 1.8V / 3.3V	CP2 MPP[5]	RSVD	A86	B86	VCC_5V_SBY		Not used
RSVD7 1.8V / 3.3V	CP2 MPP[7]	RSVD	A87	B87	VCC_5V_SBY		Not used
HCSL PCIe Gen3 compliant	100MHz clock generator	PCIE_CK_REF+	A88	B88	BIOS_DIS1#		SPI CS0/1 switch, asembly option
HCSL PCIe Gen3 compliant	100MHz clock generator	PCIE_CK_REF-	A89	B89	NCSI_RX_ER		Not used
		GND (FIXED)	A90	B90	GND (FIXED)
	3.3v power. Gated by 12v input	SPI_POWER	A91	B91	NCSI_CLK_IN		Not used
3.3V	CP0 MPP[13]	SPI_MISO	A92	B92	NCSI_RXD1		Not used
microSD CLK	CP0 MPP[56]	GPO0	A93	B93	NCSI_RXD0		Not used
3.3V	CP0 MPP[16]	SPI_CLK	A94	B94	NCSI_CRS_DV		Not used
3.3V	CP0 MPP[15]	SPI_MOSI	A95	B95	NCSI_TXD1		Not used
3.3V, assembly option	SLB9670	TPM_PP	A96	B96	NCSI_TXD0		Not used
Not used		TYPE10#	A97	B97	SPI_CS#	CP0 MPP[14] / CP0 MPP[12] selected by BIOS_DIS0#	3.3V
3.3V	AP MPP[11]	SER0_TX	A98	B98	NCSI_ARB_IN		Not used
3.3V	AP MPP[19]	SER0_RX	A99	B99	NCSI_ARB_OUT		Not used
		GND (FIXED)	A100	B100	GND (FIXED)
3.3V	CP0 MPP[50]	CAN0/SER1_TX	A101	B101	FAN_PWMOUT	CP0 MPP[39] & EMC2301	EMC2301 is assembly option
3.3V	CP0 MPP[51]	CAN0/SER1_RX	A102	B102	FAN_TACHIN	CP0 MPP[26] & EMC2301	EMC2301 is assembly option
Not used		LID#	A103	B103	SLEEP#		Not used
	12v input (9v-15v)	VCC_12V	A104	B104	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A105	B105	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A106	B106	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A107	B107	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A108	B108	VCC_12V	12V input (9v-15v)
	12v input (9v-15v)	VCC_12V	A109	B109	VCC_12V	12V input (9v-15v)
		GND (FIXED)	A110	B110	GND (FIXED)

CD Header

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes

Notes	Driving IC	Schematics Pin Name	Pin Number	Pin Number	Schematics Pin Name	Driving IC	Notes
		GND (FIXED)	C1	D1	GND (FIXED)
		GND	C2	D2	GND
Not used		USB_SSRX0-	C3	D3	USB_SSTX0-		Not used
Not used		USB_SSRX0+	C4	D4	USB_SSTX0+		Not used
		GND	C5	D5	GND
	CP2 SD[1]	USB_SSRX1-	C6	D6	USB_SSTX1-	CP2 SD[1]	Serial 100nF
	CP2 SD[1]	USB_SSRX1+	C7	D7	USB_SSTX1+	CP2 SD[1]	Serial 100nF
		GND	C8	D8	GND
Not used		USB_SSRX2-	C9	D9	USB_SSTX2-		Not used
Not used		USB_SSRX2+	C10	D10	USB_SSTX2+		Not used
		GND (FIXED)	C11	D11	GND (FIXED)
Not used		USB_SSRX3-	C12	D12	USB_SSTX3-		Not used
Not used		USB_SSRX3+	C13	D13	USB_SSTX3+		Not used
		GND	C14	D14	GND
Not used		10G_PHY_MDC_SCL3	C15	D15	10G_PHY_MDIO_SDA3		Not used
3.3V, 2.2k pull-up Can be configured as I2C	CP2 MPP[37]	10G_PHY_MDC_SCL2	C16	D16	10G_PHY_MDIO_SDA2	CP2 MPP[38]	3.3V, 2.2k pull-up Can be configured as I2C
3.3V, PTP_CP0_CLK_IN	CP0 MPP[29]	10G_SDP2	C17	D17	10G_SDP3	CP2 MPP[29]	3.3V, PTP_CP2_CLK_IN
		GND	C18	D18	GND
Not used		PCIE_RX6+	C19	D19	PCIE_TX6+		Not used
Not used		PCIE_RX6-	C20	D20	PCIE_TX6-		Not used
		GND (FIXED)	C21	D21	GND (FIXED)
Not used		PCIE_RX7+	C22	D22	PCIE_TX7+		Not used
Not used		PCIE_RX7-	C23	D23	PCIE_TX7-		Not used
3.3V, 2.2k PU	CP2 MPP[50]	10G_INT2	C24	D24	10G_INT3		Not used
		GND	C25	D25	GND
Not used		10G_KR_RX3+	C26	D26	10G_KR_TX3+		Not used
Not used		10G_KR_RX3-	C27	D27	10G_KR_TX3-		Not used
		GND	C28	D28	GND
	CP2 SD[2]	10G_KR_RX2+	C29	D29	10G_KR_TX2+	CP2 SD[2]
	CP2 SD[2]	10G_KR_RX2-	C30	D30	10G_KR_TX2-	CP2 SD[2]
		GND (FIXED)	C31	D31	GND (FIXED)
Not used		10G_SFP_SDA3	C32	D32	10G_SFP_SCL3		Not used
3.3V, 2.2k PU	CP2 MPP[35]	10G_SFP_SDA2	C33	D33	10G_SFP_SCL2	CP2 MPP[36]	3.3V, 2.2k PU
3.3V, 2.2k PU	CP1 MPP[42]	10G_PHY_RST_23	C34	D34	10G_PHY_CAP_23	CP2 MPP[31]	3.3V, RSVD31
3.3V, 2.2k PU	CP1 MPP[43]	10G_PHY_RST_01	C35	D35	10G_PHY_CAP_01	CP2 MPP[32]	3.3V, RSVD32
3.3V, 2.2k PU	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 1	10G_LED_SDA	C36	D36	RSVD	CP1 MPP[28]	3.3V, PTP_CP1_PULSE
3.3V, 2.2k PU	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 1	10G_LED_SCL	C37	D37	RSVD		Not used
3.3V, 2.2k PU	CP1 MPP[35]	10G_SFP_SDA1	C38	D38	10G_SFP_SCL1	CP1 MPP[36]	3.3V, 2.2k PU
3.3V, 2.2k PU	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 2	10G_SFP_SDA0	C39	D39	10G_SFP_SCL0	CP0 I2C1 via PCA9547AP I2C Mux @ 77 Channel 2	3.3V, 2.2k PU
3.3V, PTP_CP0_PULSE	CP0 MPP[28]	10G_SDP0	C40	D40	10G_SDP1	CP2 MPP[28]	3.3V, PTP_CP2_PULSE
		GND (FIXED)	C41	D41	GND (FIXED)
	CP1 SD[2]	10G_KR_RX1+	C42	D42	10G_KR_TX1+	CP1 SD[2]
	CP1 SD[2]	10G_KR_RX1-	C43	D43	10G_KR_TX1-	CP1 SD[2]
		GND	C44	D44	GND
3.3V, 2.2k PU, Can be configured as I2C	CP1 MPP[37]	10G_PHY_MDC_SCL1	C45	D45	10G_PHY_MDIO_SDA1	CP1 MPP[38]	3.3V, 2.2k PU, Can be configured as I2C
3.3V, 2.2k PU, shared with PHY on COM	CP0 MPP[41] (/ CP0 MPP[42])	10G_PHY_MDC_SCL0	C46	D46	10G_PHY_MDIO_SDA0	CP0 MPP[40] (/ CP0 MPP[43])	3.3V, 2.2k PU, shared with PHY on COM
3.3V, 2.2k PU	CP0 MPP[24]	10G_INT0	C47	D47	10G_INT1	CP1 MPP[50]	3.3V, 2.2k PU
		GND	C48	D48	GND
	CP0 SD[4]	10G_KR_RX0+	C49	D49	10G_KR_TX0+	CP0 SD[4]
	CP0 SD[4]	10G_KR_RX0-	C50	D50	10G_KR_TX0-	CP0 SD[4]
		GND (FIXED)	C51	D51	GND (FIXED)
	CP1 SD[5]	PCIE_RX16+	C52	D52	PCIE_TX16+	CP1 SD[5]	Serial 220nF
	CP1 SD[5]	PCIE_RX16-	C53	D53	PCIE_TX16-	CP1 SD[5]	Serial 220nF
Indicate TYPE 7#	GND	TYPE0#	C54	D54	RSVD	CP2 MPP[6]	1.8V / 3.3V, RSVD6
Not used		PCIE_RX17+	C55	D55	PCIE_TX17+		Not used
Not used		PCIE_RX17-	C56	D56	PCIE_TX17-		Not used
Not used		TYPE1#	C57	D57	TYPE2#	GND	Indicate TYPE 7#
Not used		PCIE_RX18+	C58	D58	PCIE_TX18+		Not used
Not used		PCIE_RX18-	C59	D59	PCIE_TX18-		Not used
		GND (FIXED)	C60	D60	GND (FIXED)
Not used		PCIE_RX19+	C61	D61	PCIE_TX19+		Not used
Not used		PCIE_RX19-	C62	D62	PCIE_TX19-		Not used
3.3V, RSVD56	CP2 MPP[56]	RSVD	C63	D63	RSVD	CP1 MPP[52]	3.3V, RCVR0_CLK_CP1
3.3V, RSVD27	CP2 MPP[27]	RSVD	C64	D64	RSVD	CP2 MPP[30]	3.3V, PTP_CP2_PCLK_OUT
	CP2 SD[0]	PCIE_RX20+	C65	D65	PCIE_TX20+	CP2 SD[0]	Serial 220nF
	CP2 SD[0]	PCIE_RX20-	C66	D66	PCIE_TX20-	CP2 SD[0]	Serial 220nF
		RAPID_SHUTDOWN	C67	D67	GND
Not used		PCIE_RX21+	C68	D68	PCIE_TX21+		Not used
Not used		PCIE_RX21-	C69	D69	PCIE_TX21-		Not used
		GND (FIXED)	C70	D70	GND (FIXED)
Not used		PCIE_RX22+	C71	D71	PCIE_TX22+		Not used
Not used		PCIE_RX22-	C72	D72	PCIE_TX22-		Not used
		GND	C73	D73	GND
Not used		PCIE_RX23+	C74	D74	PCIE_TX23+		Not used
Not used		PCIE_RX23-	C75	D75	PCIE_TX23-		Not used
		GND	C76	D76	GND
3.3V, RSVD37	CP2 MPP[42]	RSVD	C77	D77	RSVD	CP0 MPP[30]	3.3V, PTP_CP0_PCLK_OUT
	CP2 SD[4]	PCIE_RX24+	C78	D78	PCIE_TX24+	CP2 SD[4]	Serial 220nF
	CP2 SD[4]	PCIE_RX24-	C79	D79	PCIE_TX24-	CP2 SD[4]	Serial 220nF
		GND (FIXED)	C80	D80	GND (FIXED)
Not used		PCIE_RX25+	C81	D81	PCIE_TX25+		Not used
Not used		PCIE_RX25-	C82	D82	PCIE_TX25-		Not used
3.3V, RSVD38	CP2 MPP[43]	RSVD	C83	D83	RSVD	CP1 MPP[30]	3.3V, PTP_CP1_PCLK_OUT
		GND	C84	D84	GND
Not used		PCIE_RX26+	C85	D85	PCIE_TX26+		Not used
Not used		PCIE_RX26-	C86	D86	PCIE_TX26-		Not used
		GND	C87	D87	GND
Not used		PCIE_RX27+	C88	D88	PCIE_TX27+		Not used
Not used		PCIE_RX27-	C89	D89	PCIE_TX27-		Not used
		GND (FIXED)	C90	D90	GND (FIXED)
	CP2 SD[5]	PCIE_RX28+	C91	D91	PCIE_TX28+	CP2 SD[5]	Serial 220nF
	CP2 SD[5]	PCIE_RX28-	C92	D92	PCIE_TX28-	CP2 SD[5]	Serial 220nF
		GND	C93	D93	GND
Not used		PCIE_RX29+	C94	D94	PCIE_TX29+		Not used
Not used		PCIE_RX29-	C95	D95	PCIE_TX29-		Not used
		GND	C96	D96	GND
3.3V, RSVD55	CP2 MPP[55]	RSVD	C97	D97	RSVD	CP0 MPP[52]	3.3V, RCVR1_CLK_CP0
Not used		PCIE_RX30+	C98	D98	PCIE_TX30+		Not used
Not used		PCIE_RX30-	C99	D99	PCIE_TX30-		Not used
		GND (FIXED)	C100	D100	GND (FIXED)
Not used		PCIE_RX31+	C101	D101	PCIE_TX31+		Not used
Not used		PCIE_RX31-	C102	D102	PCIE_TX31-		Not used
		GND	C103	D103	GND
	12V input (9v-15v)	VCC_12V	C104	D104	VCC_12V	12V input (9v-15v)
	12V input (9v-15v)	VCC_12V	C105	D105	VCC_12V	12V input (9v-15v)
	12V input (9v-15v)	VCC_12V	C106	D106	VCC_12V	12V input (9v-15v)
	12V input (9v-15v)	VCC_12V	C107	D107	VCC_12V	12V input (9v-15v)
	12V input (9v-15v)	VCC_12V	C108	D108	VCC_12V	12V input (9v-15v)
	12V input (9v-15v)	VCC_12V	C109	D109	VCC_12V	12V input (9v-15v)
		GND (FIXED)	C110	D110	GND (FIXED)

Common Questions and Answers

Q: Are the I2C signals 3.3v?

A: Per the COM express specifications, all GPIO and control signals are in the 3.3v domain. Please refer to the AB and CD header description on the pull-up values of those signals.

Q: Can the SERDES lanes be configured differently than the COM express standard?

A: Yes.

Documentation

	File	Modified
Labels No labels Preview View	ZIP Archive CN9132 COM 3D-files.zip	Nov 08, 2021 by SolidRun
Labels No labels Preview View	PDF File CN9132 COM_1.1-simplified-schematics.pdf	Nov 08, 2021 by SolidRun

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