The LX2162A System on Module supports the SoC JTAG signals for use with an external debugger such as NXP’s CodeWarrior TAP. The signals are available on the board-to-board header and access must be facilated by a suitable carrier board.
Signals on B2B Connector
ARM CoreSight Connector | Name | Location |
|---|---|---|
3, 5, 9 | GND | J37-2 |
1 | VTREF | J3-15 |
2 | TMS | J3-10 |
4 | TCK | J3-12 |
6 | TDO | J3-22 |
8 | TDI | J3-16 |
10 | SRST_N | J2-19 |
Decoupling TRST_B and PORESET_B
The SoM internally connects from PORESET_B to TRST_B making it impossible to debug the first stage of boot while RCW is being loaded.
It is possible to remove 0-Ohm resistor R9320 from the SoM which results in TRST_B floating. It is located between eMMC and SPI Flash:
JTAG Header on Clearfog EVB
The Clearfog Evaluation board has soldering pads for an ARM CoreSight compatible 10-pin header labeled U3014:
Connecting CodeWarrior
TBD.