RZ/G2L and RZ/V2L SOM Hardware User Manual

Revisions and Notes 

Introduction

This User Manual relates to the SolidRun’s RZG2 series, which includes

• RZG2L Dual-core ARM A55 (1.2GHz) w Cortex-M33 (200MHz)

• RZV2L Dual-core ARM A55 (1.2GHz) w Cortex-M33 (200MHz) and Renesas Original AI Accelerator "DRP-AI" 

Overview

The SolidRun’s RZG2L/V2L family is a high-performance 64-Bit Renesas. RZ/G2 Based SOMs with Integrated GPU for Next-Gen Human-Machine Interfaces. RZV2L is adding an AI accelerator to the G2L. 

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support. 

Highlighted Features

• Ultra-small footprint SOM (47x30mm) including three board-to-board connectors (250 total pins number). 

• Renesas’s SoC supports the DUAL version. 

  • Dual Cortex A55 and up to 1.2GHz 

  • Cortex-M33 subsystem processor supports real-time tasks. 

  • Video codec (H.264). 

  • AI accelerator; DRP-AI (V2L only) 

  • High-security engines. 

  • Dual Ethernet interfaces. 

  • Up to two CAN interfaces. 

  • High industrial reliability with in-line ECC on DDR4 and on on-chip RAM. 

  • Single MIPI-CSI and single MIPI-DSI (H.264) 

  • Optional RGB interface. 

  • Two USB 2.0. 

• DDR4 memory in x16 configurations supports up to 2GB and up to 1.6GT/s. 

• Up to 128GB eMMC. 

• 1Mb QSPI NOR Flash 

• Wi-Fi 11b/g/n/ac + Bluetooth 5.0 certified module 

• 1Mb QSPI NOR Flash 

• 1Kb I2C EEPROM 

• Power management devices 

• Commercial and industrial temperature grade support. 

Supporting Products

The following products are provided by SolidRun both as production-level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard Pro – An extended board computer incorporating the SOM with different Linux distributions while adding extra hardware functionalities and access to the hardware.

Description

Block Diagram

The following figure describes the RZ/G2L Blocks Diagram.

Features Summary

Following are the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin mux table below and the Renesas datasheets): 

• Renesas’s RZG2 series SoC (Dual ARM® Cortex™ A55 Processor, up to 1.2 GHz) 

• Cortex-M33 (200MHz) subsystem processor. 

• AI accelerator; DRP-AI (V2L only) 

• Up to 2GByte DDR4 memory and up to 1.6GT/s 

• Eight bits eMMC 5.1 memory or a four bits SD interface 

• 1Kb I2C EEPROM. 

• 8Mb QSPI NOR Flash. 

• 4-lanes MIPI-DSI interface 

• Optional RGB (8,8,8) interface. 

• 3D graphics engine (Arm Mali-G31). 

• Video codec (H.264). 

• 4-lanes MIPI CSI-2  

• Dual 10/100/1000 Mbps Ethernet PHY 

• Wi-Fi (802.11a/b/g/n/ac) + BT (5.0) Murata's certified module  

• Two USB 2.0 Host and Device 

• Single eSPI interface. 

• Up to four Serial interfaces. 

• Up to 2 CAN-FD. 

• Power: 

  • A single 5.0V input using B-to-B connector. 

  • 3.3V/1A output to support carrier's digital interfaces. 

  • RAA215300 PMIC 

Core System Components

RZ/G2L SoC Family

Ideal for automation, smart buildings, network cameras, and IoT devices, SolidRun RZ/G2 SOMs combine a powerful MPU, GPU, extended ECC, Ethernet, and offer long-term Linux software support 

A verified Linux Package (VLP) reduces cost and simplifies design.

MEMORIES

The RZG2L SOM supports a variety of memory interfaces for booting and data storage. The following figure describes the RZG2L memory interfaces.

DDR4

• Up to 2GB memory space.

• 16 Bits data bus.

• Up to 1600 MT/s.

• ECC function for single-bit and double-bit error reporting, single-bit error correction, and programmable removal of ECC storage

• Support various low-power modes, clocks, and power-gated operations.

• Support Self-Refresh mode.

eMMC and SD NAND Memory

SD0 of the RZG2L/V2L can be configured as an 8-bit eMMC interface or a 4-bit SDIO. Configuration can be done during the boot process (Boot strap pins, SD0_DEV_SEL) or by SW (SD0_DEV_SEL_SW, GPIO_P22_1). 

Selecting SD0’s physical connection (eMMC or uSD card) is done by an analog switch.

 eMMC

• Up to 128GB memory space.

• 8 Bits data bus.

• Support MMC standard, up to version 4.5.1.

• Supports High-speed, HS200 transfer modes

• uSDHC-0.

• Can be used as BOOT NVM **

Micro-SD (Carrier)

• Optional on the carrier board

• uSDHC-0.

• Implements 4 data bits.

• Support SD/SDIO standard up to version 3.0.

• SD, SDHC, and SDXC SD memory card access supported.

• Default, high-speed, UHS-I/SDR50, and SDR104 transfer modes supported

• Can be used as BOOT NVM **

Quad Serial NOR Flash (SOM)

• Each channel can be configured as a 1/2/4-bit operation.

• Support both SDR (66MHz) mode and DDR (50MHz) mode

• No reset

• QSPIA/nSS0.

• Can be used as BOOT NVM **

 EEPROM (SOM)

• 1Kb EEPROM

• ON-Semi’s CAT24AA01TDI or compatible

• I2C0

• Address 0X50 (7 bits format)

• Stores SOM’s configurations.

Serial NOR Flash (Carrier)

• Optional on carrier board

• 1-bit data bus.

• eSPI1/nSS0

• Can be used as BOOT NVM *

10/100/1000 Mbps Ethernet PHY

 The SOM supports two fast Ethernet interfaces.

• RGMII interface.

• 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T.

• MaxLinear's MxL86110I PHY.

• Auto-MDIX and polarity correction.

• Energy-Efficient Ethernet (EEE) and power down mode.

• 10k byte jumbo frame support.

WI-FI (802.11AC/A/B/G/N) AND BT 5.3 (MURATA'S CERTIFIED MODULE)

WI-FI & BT

 The WI-FI & BT module is Murata’s 1MW module Based on Cypress CYW43455 chip. The WI-FI main features are:

• Operate at ISM frequency Band (2.4/5 GHz)

• IEEE Standards Support 802.11a, 802.11b, 802.11g, 802.11n, 802.11ac

• WI-FI over SDIO-1 interface

• BT 5.3 BR/EDR/LE

• BT over UART-2 Interface

• Global certification.

External Interfaces

General

The SOM incorporates three Hirose DF40 board-to-board headers.

The selection of the Hirose DF40 is due to the following criteria:

• Miniature (0.4m pitch)

• Highly reliable manufacturer

• Availability (worldwide distribution channels)

• Excellent signal integrity (supports 6Gbps)

  • Please contact Hirose or SolidRun for reliability and test result data.

• Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). RZG2L/V2L SOM’s headers are fixed, the final mating height is determined by carrier implementation

USB 2.0

The RZG2L/V2L supports two USB 2.0 interfaces. The following figure describes the USB interfaces.

The USB’s main features are:

• Single USB 2.0 OTG/DRD(Host/Function) interface (USB0)

• Single USB 2.0 Host interface (USB1).

• Support mode: High-Speed(480Mbps)/Full-Speed(12Mbps)/Low-Speed(1.5Mbps).

• OTG function (Rev2.0).

• B2B Connector’s Signal Description

• DRD (Dual-Role-Device) function (Static switch between Host and Function).

• Power control signals are not part of the USB module, any available GPIO can be used.

MIPI CSI

The following figure describes the CSI interface.

• Supports MIPI CSI-2 V2.1 and MIPI D-PHY V2.1 (80 Mbps ~ 1500 Mbps).

• Maximum image size: 5 M pixels.

• Minimum image size: QVGA (320 × 240) ＝ 76.8 K pixels.

• Maximum number of valid pixels in the horizontal direction: 2800 pixels.

• Maximum number of valid pixels in the vertical direction: 4095 lines

• Support 1/2/4 lanes.

• Support 4 Virtual Channel.

MIPI DSI

The following figure describes the DSI interface.

The DSI main features are:

• Display Serial Interface Version 1.3.1.

• Support up to Full HD (1920 × 1080), 60 fps (RGB888).

• Maximum Bandwidth: 1.5 Gbps per lane, 4 data lanes.

• Support Output Data Format: RGB666 / RGB888.

• Supports 1, 2, 3 and 4 lane configurations.

• Support for Virtual Channel

Parallel Interface

• Support WXGA (1280x800), 60 fps.

• Support Output Data Format: RGB666 / RGB888. 

• CLK / HD / VD timing signal supported. 

UART

Up to 4 UART interfaces. The following figure describes the UART interfaces.

The UART interface's main features are:

• UART 2 is connected directly to the WI-FI/BT Modem to support the BT. It is NOT available on the SOM B-t-B connector.

• UART 0 supports TX, RX and is used as terminal interface

• UART 1 supports TX, RX, CTS and RTS.

• UART 3 supports TX and RX.

• UART 3 supports TX and RX.

• Selectable bit rate with an on-chip baud rate generator.

SPI

Up to 3 SPI interfaces. The following figure describes the eSPI interface.

• Single chip select nSS0.

• Master/Slave configurable.

• Switching of the polarity of the serial transfer clock.

• Switching of the clock phase of serial transfer.

• Transfer bit-length is selectable as 8, 16, or 32 bits.

I2C

Up to 4 I2C Interfaces. The following figure describes the I2C interfaces.

The I2C main features are:

• I2C-3 is used only on the SOM. It is connected to the PMIC.

• I2C-0 is available on the connector and connected to the SOM’s EEPROM.

• I2C-1 and I2C2 are available on the BtB connectors.

• I2C bus format or SMBus format.

• Master mode or slave mode selectable

• Up to 1 Mbps.

• Up to three slave-address settings can be made.

• Internal time-out function is capable of detecting long-interval stop of the SCL (clock signal).

uSD

The uSD interface is multiplexed with the eMMC interface. Only one of them is available.

CAN-FD

Up to 2 CANFD interfaces are available. The following figure describes the CAN interfaces.

The CAN main features are:

• Supports two interface modes, classical CAN mode and CANFD mode.

• ISO11898-1 compliant.

• Maximum 1 Mbps in classical CAN mode.

• Nominal bit rate: max.1 Mbps, data bit rate: max. 4 Mbps in CANFD mode.

CONNECTOR’S SIGNAL DESCRIPTION

J5001

J7

J9

mikroBUS

LCD (Parallel Video Output) Signals allocation

Power & Reset

The RZG2L/V2L SOM power source is a single 5V source. It uses Renesas’s PMIC to source all the SOM's power rails. The following figure describes the power architecture.

The power architecture's main features are:

• Single 5V power source.

• Renesas’s RAA215300 sources the RZG2L/V2L power rails.

• 3.3V output up to 0.6A (Need to calculate system and SOM power).

• Power up sequence is supported by the PMIC configuration.

POWER CONSUMPTION

RZ/G2L Power Table:

RZ/V2L Power Table:

RESET

The PMIC generates the POR. A reset signal (PMIC_CRST_IN#) from the carrier board can generate a POR.

The PMIC supports a Power ON/OFF* signal to disable/enable all power signals besides RTC.

The PMIC supports an RTC that can be powered by a battery (J7-63).

RZG2L/V2L INTEGRATION MANUAL

POWER UP SEQUENCE

A single 5V input sources the RZG2L/V2L. The PMIC supports all power sequences.

When using the SOM 3.3V output there is no need to consider its power sequence. If an external power source is used for the 3.3V, it must be powered according to the power sequence rules. (See RZG2L/V2L datasheet for details)

BOOTING OPTIONS

Strap pins Booting

The RZG2L/V2L boost from different NVM or serial interfaces according to external resistors setting. The boot configuration is set by the three configuration signals (MD0, MD1, and MD2) and a selection signal (SD0_DEV_SEL) that select between eMMC and uSD (Mux on SOM). Below is a table describing the configuration modes. 

I2C INTERFACES

The RZG2L/V2L uses I2C2 (PMIC) interfaces for its internal configurations.

GPIO INTERFACES

The RZG2L/V2L SOM uses some GPIO signals for its internal controls. The following table describes the GPIO allocation.

Mechanical Description

Following is a diagram of the TOP VIEW of the RZG2L/V2L.

Documentation

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