CN9130 SOM Hardware User Manual
- SolidRun
- Josua Mayer
- Rabeeh Khoury
Revision and Notes
Date | Owner | Revision | Notes |
|---|---|---|---|
Sep 26, 2021 | Alon Rotman | 1.0 | Initial release information 2. Relevant for PCB revision 1.0 |
Nov 24, 2021 | Alon Rotman | 1.1 |
|
Oct 29,2023 | Rabeeh Khoury | 1.2 | Added PCB rev 1.3 3D Model in Documentation section |
Sep 02, 2024 | Josua Mayer | 1.3 | Updated AP/CP Signal usage and B2B connectors tables according to production version SoM |
Sep 10, 2024 | Josua Mayer | 1.3.1 | Updated J3 SPI/USB signals |
Sep 12, 2024 | Josua Mayer | 1.3.2 | removed invalid mating connector part number for J3 |
Sep 16, 2024 | Josua Mayer | 1.3.3 | added ptp signal descriptions |
Dec 01, 2024 | Josua Mayer | 1.4 | updated core clock signal descriptions to match pinout tables |
Table of Contents | |||
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.
Introduction
This document is intended for hardware engineers that are willing to integrate the CN9130 SOM from SolidRun ltd, into their own design.
The document provides details with regards CN9130 SOM rev 1.1.
The CN9130 SOM is pin and size compatible to the A388 SOM by SolidRun and can be used as an upgrade for the existing ClearFog Base and ClearFog Pro.
Note: the pinout of the CN9130 and A388 are slightly different due to the MPP muxing of each SoC. please review carefully the tables below
Overview
CN9130 System On Module is a highly integrated SOM module based on Marvell’s CN9130 SoC.
The SoC highlights are up to 2.2GHz with 4 Cortex A72 Arm cores, DDR4 controller and 6 high speed SERDESs.
The module integrates the following features –
CN9130 SoC (up to 2.2GHz).
On board 64bit DDR4 bus supporting up to 16GB at 2400MT/s without ECC
Single 12V or 5V DC-input is required.
Block Diagram
Specifications
Features | CN9130 SOM Specifications |
Processor Core | 4 cores Arm Cortex A72 |
Processor speed | 2.2GHz (Commercial) |
DDR | On board DDR4: |
eMMC | Up to 64GB (assembled 8GB) |
Flash | 64Mbit SPI NOR flash |
SATA 3.0 | up to 2 Ports |
Ethernet | 1x MDI using 88E1512 PHY 1x 10/5 GbE port + 2x 1/2.5 GbE Ports |
PCIe gen 3.0 | 1 Port x4 + 2 Ports x 1 |
USB 3.0 | Up to 2 x USB 3.0 (Host/Device) |
I2C | 2 |
SMI & XSMI | 2 |
UART | 2 |
PPS/PTP/Sync-E support | Untested, for authoritative information, consult Marvell documentation and Errata (available under NDA). |
SPI bus | ✓ |
RTC support | ✓ |
Power | 5V to 12V DC-input |
Supported OS | Linux kernel 5.8x Yocto DPDK UEFI KVM/QEMU/Containers NFV Openstack compute node |
Environment | Commercial: 0°C to 70°C |
Dimensions | 49mm X 35mm |
|
Compatibility between SOMs A388 and CN9130
Both SOMs have exactly the same form factor and footprint
The CN9130 SOM was designed to support SolidRun’s ClearFog Base/Pro. In case of any custom design based on A388 that wants to upgrade to CN9130, any case needs to be examined individually and review carefully the borad-to-board pinout
In the documentation section there is an excel table with exact pinout difference
Main differences due to SoC pinout:
Feature | A388 | CN9130 |
USB2.0 | 3 Ports | 2 Ports |
SATA 3.0 | 3 Ports | 2 Ports |
125MHz clock out | ✓ | X |
SD/EMMC Boot | boot from either SD or eMMC | Can boot from both SD or eMMC |
MCi interface | X | ✓ – Connector J3 |
input voltage | 5V and 3.3V | 5V |
Power Consumption
The following power consumption measurements were conducted on the following setup:
Clearfog Pro carrier board
Voltage / current measurement on v_5v0 voltage rail
No mPCIe / USB / SATA / ETH cable were connected to the carrier board
Temperature measurement was taken from linux using the following command
‘cat /sys/class/thermal/thermal_zone?/temp’Current and Voltage measured using an oscilloscope
Linux command ‘memtester 100M > /dev/null &’ ran 4 times according to core count
Linux command ‘cpuburn-krait’ is ran 4 times in background. The reason cpuburn-krait was chosen is since it can generate most heat out of the cores (the core pipeline are most utilized)
Frequency Scaling
In order to improve power efficiency and increase temperature limits, SolidRun had enabled cpu frequency scaling.
Please refer to the patch below for more information.
https://github.com/SolidRun/cn913x_build/commit/5fe77346371a230fd2468bfb11cbcc2c1ea10345
SolidRun, recommends to not disable the frequency scaling feature.
Power Measurments
The measurements below were conducted without frequency scaling, to reflect the maximum power consumption:
Test | Power [W] | Tj [degC] |
Idle u-boot | 4.6 | 50 |
idle Linux | 4.08 | 53 |
memtester 64bit 2400MT/s | 9.25 | 70 |
cpuburn-karit 4 cores at 2.2GHz | 9.3 | 70 |
CN9130 SOM extensions
The CN9130 has two extension busses of high performance, low latency and low power Marvell® MoChi interfaces (MCi). Each bus is comprised of 4x high speed differential pairs and a dedicated LVDS clock. Both busses are exposed through the SOM connector, enabling to connect 1 or 2 additional 88F8215 comprising the kits of CN9131 and CN9132 on the carrier board and extending the SERDES count from 6 to 12 or 18.
SERDES Muxing CN9130 – CP0:
Interface | SERDES Lane0 | SERDES Lane1 | SERDES Lane2 | SERDES Lane3 | SERDES Lane4 | SERDES Lane5 |
10GBASE-R/XFI |
|
| ETH_Port0 |
| ETH_Port0 |
|
5GBASE-R |
|
| ETH_Port0 |
| ETH_Port0 or ETH_Port1 |
|
10GBASE-X2 (RXAUI) |
|
| ETH_Port0 Lane 0 | ETH_Port0 Lane 1 | ETH_Port0 Lane0 | ETH_Port0 Lane 1 |
1000BASE-X (SGMII) / 2.5GBASE-X (HS-SGMII) | ETH_Port1 | ETH_Port2 | ETH_Port0 | ETH_Port1 | ETH_Port0 or ETH_Port1 | ETH_Port2 |
SATA 3.0 | SATA1 | SATA0 | SATA0 | SATA1 |
| SATA1 |
USB 3.0 HOST |
| USB 3.0 Port0 Host | USB 3.0 Port0 Host | USB 3.0 Port1 Host | USB 3.0 Port1 Host |
|
USB 3.0 Device |
| USB 3.0 Port0 Decive |
|
| USB 3.0 Port0 Decive |
|
PCIe RC/EP | PCIex4 Port0 LANE0 | PCIex4 Port0 LANE1 | PCIex4 Port0 LANE2 | PCIex4 Port0 LANE3 | PCIex1 Port1 | PCIex1 Port2 |
Assignment on Clearfog Base | SATA0 Port 1 | USB-3.0 Host Port0 | XFI ETH Port0 | SGMII ETH Port1 | USB-3.0 Host Port 1 | PCIe Gen3 Port 2 |
Assignment on Clearfog Pro | SATA0 Port 1 | USB-3.0 Host Port0 | XFI ETH Port0 | SGMII ETH Port1 | PCIe Gen3 Port 1 | PCIe Gen3 Port 2 |
The following port configuration can’t be used simultaneously:
SGMII port 0 / HS SGMII port0, RXAUI and XFI/10GBASE
SGMII port 1 and HS SGMII port 1
SGMII port 2 and HS SGMII port 2
CORE Clock BOOT Straps
PLL_SEL[0] – MPP[15] – CP_SPI1_MOSI
PLL_SEL[1] – MPP[16] – CP_SPI1_SCK
PLL_SEL[2] – MPP[17] – CP0_SYS_PLL_SEL2
PLL_SEL[3] – MPP[46] (not exposed on B2B connector, 10K pull-down on SoM)
Core Clock [MHz] | Configuration PLL_SEL [3:0] |
1600 | 0x0000 (0h0) |
2000 | 0x0010 (0h2) |
2200 | 0x0100 (0h4) |
BOOT MODE BOOT Straps
BOOT_MODE[0] – MPP18, 10K PU
BOOT_MODE[1] – MPP19, 10K PU
BOOT_MODE[2] – MPP20, 10K PD (not exposed on B2B connector)
BOOT_MODE[3] – MPP21, 10K PU
BOOT_MODE[4] – MPP22, 10K PU (not exposed on B2B connector)
BOOT_MODE[5] – MPP23, 10K PU (not exposed on B2B connector)
BOOT MODE | Configuration BOOT_MODE [5:0] |
SD Card (CP_SD) | 0b101001 (0x29) |
eMMC (AP_SD) | 0b101010 (0x2A) |
NOR Flash SPI 24 address bit (CP_SPI1) | 0b110010 (0x32) |
SD Card (CP_SD, undocumented) | 0b111001 (0x39) |
eMMC (AP_SD, undocumented) | 0b111010 (0x3A) |
CP0 MPP[62:0]
MPP # | Pin # | Pin Description | Notes |
|---|---|---|---|
AP_MPP[0] | AP10 | AP_SD_CLK | 1.8V, serial 22ohm resistor |
AP_MPP[1] | AT10 | AP_SD_CMD | 1.8V, 10K PU |
AP_MPP[2] | AP16 | AP_SD_D[0] | 1.8V, 10K PU |
AP_MPP[3] | AP18 | AP_SD_D[1] | 1.8V, 10K PU |
AP_MPP[4] | AT16 | AP_SD_D[2] | 1.8V, 10K PU |
AP_MPP[5] | AP14 | AP_SD_D[3] | 1.8V, 10K PU |
AP_MPP[6] | AP12 | AP_SD_DS | RCLK, 10K PD |
AP_MPP[7] | AT14 | AP_SD_D[4] | 1.8V, 10K PU |
AP_MPP[8] | AT12 | AP_SD_D[5] | 1.8V, 10K PU |
AP_MPP[9] | AT18 | AP_SD_D[6] | 1.8V, 10K PU |
AP_MPP[10] | AV18 | AP_SD_D[7] | 1.8V, 10K PU |
AP_MPP[11] | AY18 | AP_UA0_TXD | PD - Reset strap |
AP_MPP[12] | BA17 | AP_SD_HW_RST | 1.8V, 10K PD |
AP_MPP[19] | AW17 | AP_UA0_RXD | 3.3V thorough FXL2TD245L10X level shifter |
MPP[0] | AY38 | CP_SMI_MDIO | 1.8V |
MPP[1] | AV38 | CP_SMI_MDC | 1.8V |
MPP[2] | AW39 | CP_UA1_RXD | 3.3V thorough FXL2TD245L10X level shifter |
MPP[3] | AY40 | CP_UA1_TXD | 3.3V through FXL2TD245L10X level shifter |
MPP[4] | AW41 | CP_GPIO[4] | 1.8V |
MPP[5] | BA39 | CP_GPIO[5] | 1.8V |
MPP[6] | AW35 | CP_PTP_PULSE | 1.8V |
MPP[7] | AY36 | CP_PTP_CLK | 1.8V |
MPP[8] | BA37 | CP_PTP_PCLK_OUT | 1.8V |
MPP[9] | AW37 | NC |
|
MPP[10] | BA35 | DDR_SPD_STRAP0 | 1.8V, PU ECC / PD No ECC |
MPP[11] | AV36 | DDR_SPD_STRAP1 | 1.8V, PU 8GB, PD 4GB |
MPP[12] | AV32 | CP_SPI1_CSn[1] | 3.3V |
MPP[13] | AY34 | CP_SPI1_MISO | 3.3V |
MPP[14] | AT36 | CP_SPI1_CSn[0] | 3.3V |
MPP[15] | AT32 | CP_SPI1_MOSI | 3.3V, CPU Subsystem Clock |
MPP[16] | AV34 | CP_SPI1_SCK | 3.3V, CPU Subsystem Clock |
MPP[17] | BA29 | CP_GPIO[17] | 3.3V, PD 50k, CPU Subsystem Clock |
MPP[18] | AW29 | CP_BOOT_MODE_SEL0 | 3.3V, Boot Mode[0] |
MPP[19] | AV30 | CP_BOOT_MODE_SEL1 | 3.3V, Boot Mode[1] |
MPP[20] | BA31 | CP_BOOT_MODE_SEL2 | 3.3V, Boot Mode[2] |
MPP[21] | AT30 | CP_BOOT_MODE_SEL3 | 3.3V, Boot Mode[3] |
MPP[22] | AY30 | CP_BOOT_MODE_SEL4 | 3.3V, Boot Mode[4] |
MPP[23] | AP32 | CP_BOOT_MODE_SEL5 | 3.3V, Boot Mode[5] |
MPP[24] | AP34 | NC |
|
MPP[25] | AT34 |
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