i.MX6 SOM Hardware User Manual

Revision and Notes

Introduction

This User Manual relates to the SolidRun SOM-i.MX6 series, which includes –

Single core ARM A9 (1 GHz) of the i.MX6 SoC: SOM-i1 (C1000S-D512-FE)

Dual lite core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i2 (C1000DL-D1024-FE)

Dual core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i2eX (C1000DM-D1024-GE-W)

Quad core ARM A9 (1GHz) of the i.MX6 SoC: SOM-i4 (C1000QM-D2048-GE-W)

Overview

The SolidRun SR-SOM-MX6 is a high performance micro system on module (SOM) based on the highly integrated NXP/Freescale i.MX6 family of products.

Highlighted Features

• Ultra small footprint SOM (47x30mm) including three board-to-board connectors. Mating height is carrier board dependent.

• Freescale i.MX6 SoC (supports solo, dual lite, dual and quad versions)

  • Up to quad Cortex A9 and up to 1.2GHz

  • Integrated multi format decoders and encoders, de-interlacing and color conversion functions

  • Integrated OpenVG, OpenGL ES 2.0 and OpenCL 1.1 EP GPU

  • DDR3 memories in x32 or x64 configurations (either 2 x16 or 4 x16 on a single chip select)

• Power management devices

• Gigabit Ethernet phy based on Qualcomm Atheros 8035 (footprint compatible with 8030 fast Ethernet phy)

• Rev 1.3 – Broadcom BCM4330 based WiFi 11n and Bluetooth 4.0 (2.4GHz)

• Rev 1.5 – TI Wilink8 based WiFi 11n (up to dual MIMO 2.4GHz/5GHz) and Bluetooth 4.1 / BLE

Supporting Products

The following products are provided from SolidRun both as production level platforms and as reference examples on how to incorporate the SOM in different levels of integration:

• HummingBoard (Base/Pro/Gate/Edge) – A board computer that incorporates the SOM retains the same Linux distributions while adding extra hardware functionalities and access to the hardware.

• CuBox-i – A minicomputer that is only 2″x2″x2″ in size that runs Linux with different distribution variants, use cases.

Summary of Features

Following is the features summary of the SOM. Notice that some of the features are pinout multiplexed (please refer to the pin muxing below and the Freescale i.MX6 data sheets):

• Freescale i.MX6 series SoC (Solo/Dual Lite/Dual/Quad ARM® Cortex™ A9 Processor, up to 1.2 GHz)

• Up to 2GByte

• HDMI 1.4 interface

• LVDS display interface

• MIPI DSI

• MIPI CSI-2

• Parallel camera interface

• Parallel display interface

• 10/100/1000 Mbps Ethernet PHY

• SOM rev 1.3 – Wireless LAN 802.11 b/g/n and Bluetooth 4.0

• SOM rev 1.5 – SISO or dual MIMO 2.4 or 5GHz (depends on part) 802.11 b/g/n with Bluetooth 4.1

• 1 x USB 2.0 host and 1 x USB 2.0 OTG

• 3 x SD / MMC interfaces

• Serial interfaces

• CAN Bus

• Required power supplies –

  • One 3.3V to 5.0V interface (called in the doc VIN_5V0)

  • One 3.3V (called in the doc NVCC_EIM0)

  • One SNVS and VDDHIGH_IN power supply (called in the doc VSNVS_3V0) Notice how NVCC_EIM0 and VSNVS_3V0 can be combined into one in the HummingBoard design.

  • Optionally two SD interface power supplies (NVCC_SD2, NVCC_SD3) can be externally set to either 3.3v or 1.8v for UHS-1 support.

Block Diagram

Open

Core System Components

i.MX6 SOC Family

The Freescale i.MX6 SoC is an implementation of the ARM CortexTM-A9 core, which operates at frequencies up to 1.2 GHz. The i.MX6 provides a variety of interfaces and supports the following main features:

• Single, dual and quad processor ARM Cortex™-A9 SMP configuration. Each processor includes:

  • 32 Kbyte L1 Instruction Cache

  • 32 Kbyte L1 Data Cache

  • Private Timer and Watchdog

  • Cortex-A9 NEON MPE (Media Processing Engine) Co-processor:

  • SIMD Media Processing Architecture

    • NEON register file with 32×64-bit general-purpose registers

    • NEON Integer execute pipeline (ALU, Shift, MAC)

    • NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

    • NEON load/store and permute pipeline

  • Unified L2 cache

  • General Interrupt Controller (GIC) with 128 interrupt support

  • Global Timer

  • Snoop Control Unit (SCU)

  • Integrated Power Management unit:

    • Die temperature sensor with alarms

    • Dynamic voltage and frequency scaling for low power modes

    • Flexible clock gating control scheme

  • Graphics, Multimedia & hardware acceleration engines:

    • Video Processing Unit (VPU) – A DSP with hardware acceleration engines for video decoding and encoding

    • Image Processing Unit (IPUv3) – A hardware engine for processing images, frames, de-interlacing and various other tasks

    • 3D Graphics Processing Engine (3D GPU) – OpenGL ES 2.0 and OpenCL 1.1 EP GPU engine scalable from one shader up to 4

    • 2D Graphics Processing Engine (2D GPU) – For BitBlt function etc…

    • 2D Graphics Processing Engine (OpenVG) – OpenVG compliant GPU

    • Asynchronous sample rate converters (ASRC)

  • Security:

    • ARM TrustZone including the TZ architecture (interrupt and memory separation)

    • CAAM module – cipher acceleration and assurance module including a true pseudo random number generator (NIST certified)

    • Secure boot (HAB) and central security unit controlled via OTP fuses

  • I/O:

    • High Speed USB 2.0 OTG (Up to 480 Mbps) with integrated HS USB Phy

    • High Speed USB 2.0 HOST (Up to 480Mbps) with integrated USB phy

    • Single lane PCI-Express 2.0 (includes clock generation)

    • Misc. SD and MMC interface with 3.3v / 1.8v voltage level support (for UHS-1 speeds)

  • Misc. serial interfaces (SPI, NOR, I2S, I2C, CAN etc…)

10/100/1000 MBPS Ethernet PHY

The Ethernet PHY is based on the Qualcomm / Atheros AR8035 PHY and incorporates the following features:

• 10BASE-Te/100BASE-TX/1000BASE-T IEEE 802.3 compliant

• 1000BASE-T PCS and auto-negotiation with next page support

• IEEE 802.3az EEE

• Green ETHOS power saving modes with internal automatic DSP power-saving scheme

• SmartEEE

• Wake on LAN

• Automatic MDI/MDIX crossover and polarity correction

• IEEE 802.3u compliant auto negotiation

• Cable Diagnostic Test (CDT)

The PHY is connected via the i.MX6 RGMII interface.

BCM 4330 Based (SOM Rev 1.3) – Wireless LAN 802.11 B/G/N & Bluetooth 4.0 SiP

The system in package (SiP) is based on the AzureWave AW-NH660 module and incorporates the following features:

• BCM4330 WiFi / BT based

• WiFi / BT co-existence support

• WiFi :

  • Integrated CPU with on-chip memory for complete WLAN subsystem minimizing the need to wake up the application processor

  • SDIO based interface (connected via the i.MX6 SD1 interface)

  • Single band 2.4 GHz 802.11 b/g/n

  • Supports IEEE 802.11d, e, j, I, j, r, k, w

  • WEP, WPA/WPA2, AES, TKIP, CKIP (SW) based security

  • WMM/WMM-PS/WMM-SA

  • Proprietary protocols – CCXv2/CCXv3/CCXv4/CCXv5, WFAEC

• Bluetooth:

  • Fully supports Bluetooth 4.0 + EDR (AFH, QoS, eSCO, fast connect, SSP, SSR, EPR, EIR, LST)

  • High speed UART (max 4Mbps) and PCM for Bluetooth support (connected via
    i.MX6 UART4 interface and i.MX6 AUD3 audio PCM interface)

  • HS packet types, class 1 or class 2 transmitter type operation

TI WiLink8 Based(SOM Rev 1.5) – Wireless LAN 802.11 B/G/N & Bluetooth 4.1 SiP

The SiP (System in package) incorporates the following features –

• TI Wilink 8 WiFi / BT based

• WiFi / BT co-existence support

• WiFi :

  • Integrated RF front end, power amplified, DC-DC, crystal, switches, filters and
    power management

  • SDIO based interface (connected via the i.MX6 SD1 interface)

  • 2.4 GHz or 5 GHz (depending on model) 802.11 a/b/g/n

  • SISO or MIMO (two antennas)

  • 20 and 40 MHz channels on 2.4/5 GHz bands

  • Wi-Fi direct multi-role multi-channel

  • Up to 10 clients supported in AP role

• Bluetooth:

  • Fully supports Bluetooth 4.1 + EDR including Bluetooth low energy

  • High speed UART (max 4Mbps) and PCM for Bluetooth support (connected via
    i.MX6 UART4 interface

i.MX6 SOM Interfaces

i.MX6 SOM- External Interfaces Brief

The SOM incorporates three Hirose DF40 board-to-board headers. The selection of the Hirose DF40 is due to the following criteria:

• Miniature (0.4m pitch)

• Highly reliable manufacturer

• Availability (worldwide distribution channels)

• Excellent signal integrity (supports 6Gbps)

  • Please contact Hirose or SolidRun for reliability and test result data.

• Mating height of between 1.5mm to 4.0mm (1.5mm to 3.0mm if using 70-pin Board-to-Board header). SR-SOM-MX6 headers are fixed, the final mating height is determined by carrier implementation

The different board-to-board functionality is defined as follows:

• Main 80 pin B2B. Includes the following functionality:

  • Main supply +3.3v to +5.0v in (5 pins)

  • I/O supply +3.3V and SD2, SD3 supplies (can be fixed +3.3V or externally switched +3.3V / 1.8V to support UHS-1)

  • Ethernet MDI (4 differential pairs), LED activity or link (10/100/1000) and Ethernet TCT

  • SATA TX/RX (2 differential pairs) – Functional on i.MX6 dual and quad (not supported on solo / dual lite)

  • USB OTG and HOST (2 differential pairs)

  • Various GPIOs and pins that can be muxed. By default, it is configured to be 2xI2C, PWMs (1 through 4), SPI 2, SD2 interface and USB enable.

• Second 80 pin B2B. The board-to-board exposes the following functionality:

  • System power on reset

  • HDMI 1.4 (4 differential pairs), CEC, +5V boosted I2C and HDMI HPD

  • PCI express 2.0 (3 differential pairs include TX/RX and clock)

  • USB OTG charge detect and USB OTG ID

  • MIPI CSI 2 (3 differential pairs for solo / dual lite and 5 differential pairs for dual / quad versions)

  • MIPI DSI (3 differential pairs)

  • LVDS 0 (5 differential pairs)

  • UART1 (typically used for main system debug port)

  • Various GPIOs and pins that can be muxed. By default, it is configured to be AUD5 I2S interface, CCM CLKO1/CLKO2, SD2 voltage select, SPDIF out, USB HOST / OTG over current indication.

• Third 70 pin B2B. This board-to-board exposes the following functionality:

  • Power management (EIM_WAIT, TAMPER, PMIC standby, MX6_ONOFF, PMIC_ON_REQ)

  • Boot mode override

  • MLB interface (marked as reserved on rev 1.3 and not available on rev 1.5. Contact SolidRun about availability of i.MX6 SOM with MLB interface)

  • Various GPIOs and pins that can be muxed. By default it is configured to be UART3, SPDIF in, Display and camera parallel interface, UART2, Watchdog timer, SD3 and SD4 interfaces)

SR-SOM-MX6 ON Board Functions

10/100/1000 Mbps PHY

The SOM incorporates a Qualcomm / Atheros AR8035 PHY. The PHY connectivity is as follows:

• Uses 2.5V interface voltage level

• RGMII (optional AR8030 with RMII)

• Phy reset function via i.MX6 pad V5 (KEY_ROW4). Active low

• Default phy address either 0x0 or 0x4 (depends on LED activity reset strap, either pulled down or pulled up)

802.11 b/g/n and Bluetooth SiP

The SOM incorporates AzureWave AW-660 SiP or TI Wilink8 SiP. The SiP interfaces are:

• WiFi connectivity via i.MX6 SDIO1

• Bluetooth connectivity via i.MX6 UART4

• Audio PCM connectivity via i.MX6 AUD3

• Antenna via onboard UFL connector

i.MX6 SOM External Interfaces Detailed Description

As previously described, the SOM incorporates three Hirose DF40 based board-to-board headers.

The SOM uses the header of these board-to-board connectors which is fixed in height, while the mating height is determined by the carrier, by using different Hirose DF40 receptacle mating heights (1.5 to 4.0mm) (1.5mm to 3.0mm if using 70-pin Board-to-Board header).

J5002 Board to Board Header Pin Description

This board-to-board header uses Hirose DF40 DH40C-80DP-0.4V(51) header. The pin description may be found in the following tables:

J8004 Board to Board Header Pin Description

J5001 Board to Board Header Pin Description

i.MX6 SOM Power Up Sequence

Integration with the SR-SOM-MX6 is easy, power sequencing wise. Note the following requirements:

• The SOM internal power management contains a soft-start clamp that gradually raises its internally generated power supplies once VIN_5V0 is applied. The soft-start timing is set to be 800us (typ.). SNVS_3V0 must be applied well ahead of the internal power rails. We recommend that SNVS_3V0 be applied no later than 200uS after

• SNVS_3V0 must be applied before NVCC_EIM0, NVCC_SD2 and NVCC_SD3. Alternatively, SNVS_3V0 can be shorted with those power supplies as long as they do not exceed 3.3v (absolute maximum including overvoltage ripples).

• Notice that a cost saving practice when integrating SR-SOM-MX6 is to have a single DC-DC of output voltage 3.2v, and -+100mV ripple that supplies all the SR-SOM-MX6 supplies, except the USB_OTG_VBUS and USB_HOST_VBUS which are 5V when

i.MX6 SOM GPIO (Internal) Boot Source Configuration

1. MX6 is very flexible when it comes to selecting the boot source. This section describes how to set pull up /down on the carrier board in order to perform boot indicated by GPIOs

Blowing the device’s eFuses is alternative to using GPIOs in order to set boot source. This topic is widely covered on the SolidRun eFuses for i.MX6 SOM (Developers page) .

The following are the general instructions on how to perform boot from different common sources, the guideline in general is the following –

1. BOOT_CFGx[7:0] is pulled down in reset and then reverts to pull up.

2. The user should pull up the required pins, but making sure that all pins in the bus are either floating, tri-stated in reset (POR_B) or pulled down.

Since the above forces the user to pull up/down the entire bus, below are more pervasive examples of 3 different boot sources used as in HummingBoard Edge Quick Start Guide :

• SDHC2 SD

• SDHC3 eMMC

• SATA

Boot from SDHC2 External SD Card 

The following is an example of booting from SD card through schematics signals SD2_*:

The following must be pulled up (10 kohm or lower):

The other signals in BOOT_CFG3 and BOOT_CFG4 that are not defined in the above two tables do not affect this boot method.

Boot from SDHC3 eMMC

The following is an example of booting SD card through schematics signals SD3_*:

The following must be pulled up (10 kohm or lower):

The other signals in BOOT_CFG3 and BOOT_CFG4 that are not defined in the above two tables do not affect this boot method.

Boot from SATA

The following must be pulled up (10 kohm or lower):

The other signals in BOOT_CFG1, BOOT_CFG2, BOOT_CFG3 and BOOT_CFG4 that are not defined in the above two tables do not affect this boot method.

Rev 1.3 Debugging Capability

 Rev 1.3 of SR-SOM-MX6 exposes two main debugging interfaces:

1. UART interface

2. JTAG interface

The UART interface is a null modem interface that is internally pulled up to two different voltage levels:

1. NVCC_EIM0 voltage in case AzureWave SiP is not used (typically 3V)

2. 8v when the AzureWave SiP is used (signals are shared with SDIO interface that is limited to 2.8V)

The UART interface is optional to use and mentioned here since most of the software infrastructure used in CuBox-i and HummingBoard uses those two signals for debugging.

JTAG interface is on the SR-SOM-mx6 and is exposed as test pins. Following is a snapshot of the test points and its connectivity traces:

Open

Rev 1.5 Debugging Capability

Rev 1.5 of SR-SOM-MX6 exposes the UART interface which is the main debugging interface. The UART interface is a null modem interface.

Differences Between SOM Versions

Changes Between SOM Rev 1.0 to Rev 1.2

Moved VDD_HIGH_IN power rail from NVCC_EIM0 power pin to SNVS_3V0 power pin.

Changes Between SOM Rev 1.2 to Rev 1.3

Added three mechanical holes for RF cage to cover BRCM4330 based WiFi/BT SiP.

Changes Between SOM Rev 1.3 to Rev 1.5

Refer to PCN #20160901000 on SolidRun’s wiki pages for more details, the highlights are –

1. Replaced BCM4330 based SiP with TI Wilink8

2. Added optional eMMC. Note that if the SOM has eMMC assembled then the SD3_* signals are not routed to the board-to-board headers but are used locally for the eMMC on the SOM.

Typical Power Consumption

The following power measurements were performed on a CuBox-i4pro based system, where the main supply is 5V and internally a 5V to 3.3V LDO is being used on the carrier board (refer to CuBox-i rev-1.1 schematics).

The CuBox-i4pro incorporates the quad processor at 1GHz, 2GByte of DDR3 memory, gigabit Ethernet PHY and the WiFi and Bluetooth chipset.

Figure 6 Typical Power Consumption: CuBox-i4pro

Notes:

1. CuBox-i uses an LDO that provides 5V to 3.3V conversion that feeds the Ethernet PHY on the SOM. Due to that, the addition of 100mA on the 3.3V rail when PHY is set to 1Gbps, adds 100mA consumption on the 5.0V power rails.

2. Notice the power difference between the same workload while Tjunction of the die is 55c and 87c (~110mA difference from the 5V power rail).

1. This is using Linux suspend to memory when the front LED is off. This consumption is mainly due to DDR entering self-refresh (2GByte) and some consumption on the 3.3V LDO and leakage on the processor and SoC digital part rails.

imx6 SOM Power Consumption

Maximum Rating

Following are the maximum ratings on different power signals and power rails.

1. AR8035 Gigabit Ethernet PHY consumes 150mA out of those in a 100-meter cable configuration.

2. This is reduced to 150mA when the AR8035 is not active.

3. Assumes ultra-high speed: 1.8v, 100MHz clock rate and double data rate on data; 4-bit data on SD2 and 8-bit data on SD3.

4. Assumes VIN_5V0 = 5v. When supplying less than 5V, the maximum current increases accordingly; it is recommended to add additional margins on current limit.

5. SR-SOM-MX6 rev 1.5 incorporates TI WiLink8 based device vs. BCM4330. This adds 285mA on the NVCC_EIM0 but remove 200mA requirement from VIN_5V0.

Mechanical Description 

Following is a diagram of the TOP VIEW of the i.MX6 SOM:

Note the following details:

• The carrier board must use the same footprint as in the above mechanical

• J5002 is the main board-to-board header (bottom side in the diagram).

• J8004 is the second board-to-board header (upper side in the diagram).

• J5001 is the third board-to-board header (right side in the diagram).

• CuBox-i design does not use the mechanical holes, since the mating strength of two Hirose DF40 pairs and the internal heat spreader is satisfactory for the design requirements.

• In case 1.5mm mating height was chosen, then the SR-SOM-MX6 requirement would be that all area beneath it on the carrier will be all dedicated ONLY for the board-to-board connectivity; no other components are allowed. In case higher mating is chosen, then 1.5mm should be reserved for the SR-SOM-MX6. For instance, if 3.5mm mating height is chosen, then 1.5mm is dedicated to the SR-SOM-MX6 print side components and the remaining 2mm for the carrier components underneath the SR-SOM-MX6.

Refer to SolidRun HummingBoard and CuBox-i design and layout, where there are examples of the main and second 80 pin header board-to-board usage.

Documentation

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