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The voltage on VBUS is 5V.
There are decupling capacitors on the SOM.
PCIe
TBD
MIPI CSI
MIPI CSI interface 1 is available on the BtB connector (See MIPI CSI-2 SOM’s Camera Interface).
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The Hailo 15 SOM supports a single dual channel I2S controller.
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The Audio main features are:
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Connector’s Signal Description
J5001
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J7
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J9
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Power & Reset
Power Architecture
The Hailo 15’s power is a single 5V source. It uses Discreet power converters to generate its power rails. The following figure describes the power architecture and power up sequencing.
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The power architecture main features are:
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The Hailo 15 uses I2C0 interface for its internal configurations.
The Hailo 15 uses I2C0 interface for its internal configurations.
Ref. | Chip | I2C Port | Address A | Port | Description | |||||||
U5 | IO EXPANDER | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | RW | 74H | Enable parts on the SOM |
U12 | EEPROM | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | RW | 50H | SOM ID |
U6 | PCIe CLK GEN. |
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0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | RW | 48H | PCIe clock generator | ||
U16 | 0P8V Core PWR | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | RW | 40H | Buck control |
J2 | Leopard Camera | 0 | Check camera datasheet. |
I2C0 is available only on the SOM.
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The Hailo 15 uses some GPIO signals for its internal controls. Some of the signals are of the CPU and others are of the IO Expender. The following table describes the GPIO allocation.
Signal | I/O | Description | Remarks |
H_GPIO_6 | H_GPIO_6 | Reset the IO Expander | Active Low |
H_GPIO_8 | H_GPIO_8 | IO Expander interrupt | Active Low |
WL_REG_ON | IO_EXP 0-1 | Enable the WIFI radio | Active High |
BT_REG_ON | IO_EXP 0-2 | Enable the BT radio | Active High |
ETH_RST# | IO_EXP 0-3 | Reset the Ethernet PHY | Active Low |
ENET_nINT | IO_EXP 0-4 | Ethernet PHY interrupt | Active Low |
QSPI_SEL | IO_EXP 0-4] | Select the QSPI interface | “0” FLASH memory “1” Board to Board conn. |
Hailo 15 SOM Debugging Capability
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Hailo 15 Typical Power Consumption
TBD
Hailo 15 SOM Mechanical Description
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Federal Communications Commission (FCC) Statement
TBD