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Revision and Notes

Date

Owner

Revision

Notes

18 Feb 2018

Noam Weidenfeld

1.0

Initial release

01 Aug 2019

Noam Weidenfeld

1.1

Revision update

31 Oct 2023

Shahar Fridman

1.2

Add Power Consumption Measurement

Table of Contents

minLevel	1
maxLevel	7

Info

Disclaimer

No warranty of accuracy is given concerning the contents of the information contained in this publication. To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by SolidRun Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document. SolidRun Ltd. reserves the right to change details in this publication without prior notice. Product and company names herein may be the trademarks of their respective owners.

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B2B Connector’s Signal Description

J5001

PIN	PWR	Main	GPIO	PIN	PWR	Main	GPIO
1	3V3	PMIC_ON		2
3	3V3	BOOT_MODE0		4		DSI_DN3
5	3V3	BOOT_MODE1		6		DSI_DP3
7	GND	GND		8	GND	GND
9		DSI_CKP		10	GND	GND
11		DSI_CKN		12		DSI_DN0
13	GND	GND		14		DSI_DP0
15		DSI_DN2		16	GND	GND
17		DSI_DP2		18		PCIE1_REF_CLKP_CN
19	GND	GND		20		PCIE1_REF_CLKN_CN
21		DSI_DN1		22	GND	GND
23		DSI_DP1		24	3V3	PCIE_nPME	gpio3.IO[5]
25	GND	GND		26	3V3	PCIe_nWAKE	gpio3.IO[12]
27	3V3	PWM1_OUT		28	3V3	USB1_SS_SEL	gpio3.IO[15]
29	3V3	UART3_TXD	gpio5.IO[27]	30	GND	GND
31	3V3	UART3_RXD	gpio5.IO[26]	32		PCIE1_TXP_C
33	GND	GND		34		PCIE1_TXN_C
35				36	GND	GND
37	3V3	UART3_CTS	gpio5.IO[9]	38		PCIE1_RXP_C
39	3V3	UART3_RTS	gpio5.IO[10]	40		PCIE1_RXN_C
41	3V3	SAI1_TXD2 (BT_CFG10)	gpio4.IO[14]	42	GND	GND
43	3V3	DSI_TS_nINT	gpio5.IO[7]	44	3V3	UART2_RXD	gpio5.IO[24]
45				46	3V3	UART2_TXD	gpio5.IO[25]
47	GND	GND		48	3V3	UART2_CTS	uart4.RX/gpio5.IO[28]
49				50	3V3	UART2_RTS	uart4.TX/gpio5.IO[29]
51		SAI1_TXD4 (BT_CFG12)	gpio4.IO[16]	52	GND	GND
53		WIFI_DP		54		CSI_P1_DN0
55		WIFI_DN		56		CSI_P1_DP0
57	GND	GND		58	GND	GND
59		CSI_P1_CKP		60		CSI_P1_DP2
61		CSI_P1_CKN		62		CSI_P1_DN2
63	GND	GND		64	GND	GND
65		CSI_P1_DP3		66		CSI_P1_DP1
67		CSI_P1_DN3		68		CSI_P1_DN1
69	GND	GND		70	GND	GND

J7

PIN	PWR	Main	GPIO	PIN	PWR	Main	GPIO
1		PCIE2_REF_CLKP_CN		2		PCIE2_RXN
3		PCIE2_REF_CLKN_CN		4		PCIE2_RXP
5	GND	GND		6	GND	GND
7		PCIE2_TXN		8	3V3	SAI3_MCLK	gpio5.IO[2]
9		PCIE2_TXP		10	3V3	SAI3_RXC	gpio4.IO[29]
11	GND	GND		12	3V3	SAI1_TXC	gpio4.IO[11]
13	3V3	SAI3_TXFS	gpio4.IO[31]	14	3V3	SAI3_TXC	gpio5.IO[0]
15	3V3	SAI3_RXFS	gpio4.IO[28]	16	3V3	SPDIF_TX	gpio5.IO[3]
17	GND	GND		18	3V3	IR_CAP	gpio1.IO[12]
19		HDMI_TXP2		20	3V3	SAI1_TXD7 (BT_CFG15)	gpio4.IO[19]
21		HDMI_TXN2		22	3V3	SAI1_TXD0 (BT_CFG8)	gpio4.IO[12]
23	GND	GND		24	3V3	SAI1_TXD1 (BT_CFG9)	gpio4.IO[13]
25		HDMI_TXP1		26	3V3	SAI3_RXD	gpio4.IO[30]
27		HDMI_TXN1		28	3V3	SAI1_TXD3 (BT_CFG11)	gpio4.IO[15]
29	GND	GND		30	3V3	SAI1_TXFS	gpio4.IO[10]
31		HDMI_TXP0		32	3V3	nWDOG	gpio1.IO[2]
33		HDMI_TXN0		34
35	GND	GND		36	3V3	SAI1_MCLK	gpio4.IO[20]
37		HDMI_CLKP		38	3V3	CLKO2	gpio1.IO[15]
39		HDMI_CLKN		40
41	GND	GND		42	GND	GND
43	3V3	HDMI_CEC		44		Tanya	gpio5.IO[21]
45	5V	HDMI_DDC_SCL		46		SAI1_RXD7 (BT_CFG7)	gpio4.IO[9]
47	5V	HDMI_DDC_SDA		48	GND	GND
49	5V	HDMI_HPD		50	3V3	SAI1_RXD5 (BT_CFG5)	gpio4.IO[7]
51	3V3	SAI2_TXC	gpio4.IO[25]	52	3V3	UART1_TXD	gpio5.IO[23]
53	3V3	SAI2_TXD	gpio4.IO[26]	54	3V3	UART1_RXD	gpio5.IO[22]
55	3V3	SAI2_TXFS	gpio4.IO[24]	56	3V3	USB1_ID
57	3V3	SAI2_RXD	gpio4.IO[23]	58	GND	GND
59	3V3	SAI2_MCLK	gpio4.IO[27]	60		USB2_RXP
61	GND	GND		62		USB2_RXN
63	3V3	SAI1_RXD6 (BT_CFG6)	gpio4.IO[8]	64	GND	GND
65	3V3	SYS_nRST		66		USB2_TXN
67	3V3	SAI1_RXD4 (BT_CFG4)	gpio4.IO[6]	68		USB2_TXP
69	3V3	SAI1_RXC	gpio4.IO[1]	70	GND	GND
71	3V3	SAI1_RXFS	gpio4.IO[0]	72	3V3	SAI1_RXD2 (BT_CFG2)	gpio4.IO[4]
73	3V3	SD2_VSELECT	gpio1.IO[4]	74	3V3	SAI1_RXD3 (BT_CFG3)	gpio4.IO[5]
75	GND	GND		76	GND	GND
77		HDMI_AUXP		78	3V3	SAI1_RXD0 (BT_CFG0)	gpio4.IO[2]
79		HDMI_AUXN		80	3V3	SAI1_RXD1 (BT_CFG1)	gpio4.IO[3]

J9

PIN	PWR	Main	GPIO	PIN	PWR	Main	GPIO
1		MDI_TRXN3		2	GND	GND
3		MDI_TRXP3		4		USB1_TXP
5	GND	GND		6		USB1_TXN
7		MDI_TRXN2		8	GND	GND
9		MDI_TRXP2		10		USB1_RXP
11	GND	GND		12		USB1_RXN
13		MDI_TRXN1		14	GND	GND
15		MDI_TRXP1		16		USB1_DP
17	GND	GND		18		USB1_DN
19		MDI_TRXN0		20	GND	GND
21		MDI_TRXP0		22		USB2_DP
23	GND	GND		24		USB2_DN
25	3V3	LED_10_100_LED_1000		26	GND	GND
27	3V3	LED_ACT		28	3V3	USB_H1_PWR_EN	gpio3.IO[4]
29	3V3	PPS		30	3V3	USB_OTG_PWR_EN	gpio3.IO[2]
31	3V3	I2C3_SCL	gpio5.IO[18]	32	3V3	ECSPI2_SS0	gpio5.IO[13]
33	3V3	I2C3_SDA	gpio5.IO[19]	34	3V3	DSI_EN	gpio5.IO[6]
35	GND	GND		36	GND	GND
37	3V3	CSI_nRST	gpio1.IO[6]	38	3V3	SD2_CLK	gpio2.IO[13]
39	3V3	AUD_nMUTE	gpio1.IO[8]	40	3V3	SD2_CMD	gpio2.IO[14]
41	3V3	CLKO_25MHz	gpio3.IO[11]	42	3V3	SD2_DATA0	gpio2.IO[15]
43	5V	USB1_VBUS		44	3V3	SD2_DATA1	gpio2.IO[16]
45	3V3	ECSPI2_MISO	gpio5.IO[12]	46	3V3	SD2_DATA2	gpio2.IO[17]
47	3V3	ECSPI2_MOSI	gpio5.IO[11]	48	3V3	SD2_DATA3	gpio2.IO[18]
49	3V3	ECSPI2_SCLK	gpio5.IO[10]	50	3V3	SD2_nCD	gpio2.IO[12]
51	3V3	I2C2_SDA	gpio5.IO[17]	52	5V	USB2_VBUS
53	3V3	I2C2_SCL	gpio5.IO[16]	54	3V3	SAI1_TXD5 (BT_CFG13)	gpio4.IO[17]
55	3V3	SWDCLK1		56
57	3V3	CLK_25M		58
59	3V3	SWDIO1		60
61	1.8/3.3V	NVCC_SD2		62	3V3	ONOFF
63	3V3	3V3_OUT		64	3V3	SAI1_TXD6 (BT_CFG14)	gpio4.IO[18]
65	3V3	3V3_OUT		66
67	3V3	3V3_OUT		68	3V3	PWM2_OUT	gpio1.IO[13]
69	3V3	3V3_OUT		70	GND	GND
71	5V	VIN_5V0		72	GND	GND
73	5V	VIN_5V0		74	GND	GND
75	5V	VIN_5V0		76	GND	GND
77	5V	VIN_5V0		78	GND	GND
79	5V	VIN_5V0		80	GND	GND

Power and Reset

The i.MX8M power is a single 5V source. It uses NXP’s PMIC and discreet power converter to source all the i.MX8M power rails. The following figure describes the i.MX8M power architecture.

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Single 5V power source.
NXP’s PF4210 source most of the IMX-8 power rails.
Two discrete DC-to-DC converters source the CPU SOC and ARM powers.
SNVS_3V3 can’t be power by a battery (No separate input).
3.3V output up to 2A (Need to calculate system and SOM power).
Power up sequence is supported by the PMIC configuration.

Power Consumption

Mode	Voltage	Current	Power
Idle, Linux up	5V	324mA	1.62W
Linux up, wifi connected to 2.4GHz and sending packets by iperf3	5V	480mA	2.4W
Linux up, wifi connected to 5GHz and sending packets by iperf3	5V	576mA	2.88W
Linux up, scanning for bluetooth device	5V	336mA	1.68W
Linux up, GPU stress by glmark2	5V	660mA	3.3W
Linux up, CPU stress to maximum	5V	660mA	3.3W
All utilities are active in the same time (Wifi, GPU stress, CPU stress, Bluetooth)	5V	924mA	4.62W

Reset

The i.MX8M POR signal is activated by the PMIC output. The following figure describes the reset architecture.

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The i.MX8 SOM uses I2C1 interface for its internal configurations. The following table describes the address mapping.

Ref.	Chip	I2C Port	Address A								Port	Address B	Description

U15	PMIC	1	0	0	0	1	0	0	0	RW	08H		IMX8 PMIC
U17	EEPROM	1	1	0	1	0	0	0	0	RW	50H		EEPROM

GPIO Interfaces

The i.MX8M SOM uses some GPIO signals for it internal controls. The following table describes the GPIO allocation.

Signal	I/O	Description	Remarks
PCIE1_nCLKREQ	gpio5.IO[20]	Input from WI-FI module	Active Low
WL_REG_ON	gpio5.IO[5]	Enable the WI-FI RF	Active High
WL_nPERST	gpio4.IO[21]	Reset the WI-FI module	Active Low
REF_CLK_32K	gpio3.IO[3]	32K clock for the WI-FI module	N.I.U.
UBLOX_RSTN	gpio5.IO[1]	Reset the BT module	Active Low
ENET_nRST	gpio1.IO[9]	Ethernet PHY reset	Active Low
ENET_WoL	gpio1.IO[10]	Ethernet Wake-Up signal	Active Low
ENET_nINT	gpio1.IO[11]	Ethernet interrupt	Active Low
PMIC_nINT	gpio1.IO[7]	PMIC interrup	Active Low

i.MX8M SOM Debugging Capability

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